Dual G3's in Umax S900?

Dual G3's in Umax S900?

[Robert E Brose II]

I have just dropped a PowerLogix g3/400 in place of the 233 mhz 604e
in a Umax S900 and it's working great. What I'm wondering is
if the SMP in the recent kernels would be able to handle a second
g3/400? (The PL g3/400 board is so small that a second one would fit
into the second CPU slot on the S900 which wasn't the case for
normal 604e boards).

Thanks,
Bob
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Re: Dual G3's in Umax S900?

[Benjamin Herrenschmidt]

>
>I have just dropped a PowerLogix g3/400 in place of the 233 mhz 604e
>in a Umax S900 and it's working great. What I'm wondering is
>if the SMP in the recent kernels would be able to handle a second
>g3/400? (The PL g3/400 board is so small that a second one would fit
>into the second CPU slot on the S900 which wasn't the case for
>normal 604e boards).

No. Doing SMP with G3s is a terrible nightmare as those CPUs don't
have the necessary coherency protocols.

Ben.

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Re: Dual G3's in Umax S900?

[Holger Bettag]

Benjamin Herrenschmidt <benh@kernel.crashing.org> writes:


> No. Doing SMP with G3s is a terrible nightmare as those CPUs don't
> have the necessary coherency protocols.
>
Is MEI not enough for Linux? Instruction cache coherency problems? Or is it
because of the rudimentary implementation of tlbie/tlbia? Just curious.

  Holger


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Re: Dual G3's in Umax S900?

[Benjamin Herrenschmidt]

>> No. Doing SMP with G3s is a terrible nightmare as those CPUs don't
>> have the necessary coherency protocols.
>>
>Is MEI not enough for Linux? Instruction cache coherency problems? Or is it
>because of the rudimentary implementation of tlbie/tlbia? Just curious.

I don't have all in mind, from memory, the lack of bus broadcast for tlbie
is one, the lack of bus coherency for cache inval is another, but I am not
sure.

I think in the past, we used to have BeBox (dual 603) working, which I suppose
is pretty similar, but still hell. No way I support that for pmac kernels.

Ben.


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Re: Dual G3's in Umax S900?

[Robert E Brose II]

User Benjamin Herrenschmidt says:
> >> No. Doing SMP with G3s is a terrible nightmare as those CPUs don't
> >> have the necessary coherency protocols.
> >>
> >Is MEI not enough for Linux? Instruction cache coherency problems? Or is it
> >because of the rudimentary implementation of tlbie/tlbia? Just curious.
>
> I don't have all in mind, from memory, the lack of bus broadcast for tlbie
> is one, the lack of bus coherency for cache inval is another, but I am not
> sure.
>
> I think in the past, we used to have BeBox (dual 603) working, which I suppose
> is pretty similar, but still hell. No way I support that for pmac kernels.
>
> Ben.

I assume then that the 604e has what's needed because IBM has RS6ks with
multiples of these??

Bob
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Re: Dual G3's in Umax S900?

[Cort Dougan]

Those are definitely not SMP chips.  The lack of the tlbie broadcast is a
killer.  I did some work with a dual 750 and implemented the software
broadcast in software (the code is still in the kernel - but unused) and it
was a nightmare of inefficiency.  In most benchmarks it turned out to be a
net negative to use the second processor.

Please... please, make the world a safer place for us on the verge of
insanity OS people and don't do a SMP 750!

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Re: Dual G3's in Umax S900?

[Cort Dougan]

You're good to go with the 604's.  They're sane PPC's.  The 750's were the
only ones that got involved with the no-SMP whackiness.

} I assume then that the 604e has what's needed because IBM has RS6ks with
} multiples of these??

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Re: Dual G3's in Umax S900?

[Benjamin Herrenschmidt]

>I assume then that the 604e has what's needed because IBM has RS6ks with
>multiples of these??

Yes, and G4 as well.

Ben.


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