Low memory on Virtex-II Pro

Low memory on Virtex-II Pro

[Kerl, John]

Hello all,

There have been some recent posts about Linux & Virtex-II Pro
(FPGA with PPC405 hard core).  & apparently people have it working.

One question before I start, though:

Of course the kernel starts at *virtual* address 0xc0000000, regardless
of the processor.  But my understanding is that certain processors have
zero-based *physical* addresses for RAM, and some don't -- x86 of course
being an example of the former, and ARM being an example of the latter.
I believe that PPC is an example of the former.  Certainly our MPC857T
board, and all the other boards of which I'm aware, have RAM starting at
physical address 0x00000000.

Now, on our custom Virtex-II Pro board, with Xilinx EDK setup, there's a
bit (the MSB) in the physical address that specifies whether a memory
region is on the LMB bus or OPB bus.  We get to pick *which* bit, but
there must be *a* bit set for the SDRAM.  The upshot is that our SDRAM
starts at physical address 0xb0000000.  It can't be placed at address 0.
And block RAM could be made low, but I can't see having megabytes of
block RAM.

So, I think I have to have the kernel at non-zero physical address
with PPC405.

Can anyone advise on success or failure of doing so?

** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

Re: Low memory on Virtex-II Pro

[Peter Ryser]

John,

please correct me if I see this wrong but it looks like you are mixing up
MicroBlaze and PowerPC. The LMB is a bus that is only available on MicroBlaze.
Linux does not have support for MicroBlaze.

However, Linux works great on the PowerPC inside the Virtex-II Pro FPGA when
you map the main memory at address zero. When using EDK to build your system
just set the BASEADDR for the SDRAM to zero.

You might also want to be aware of the fact that the interrupt controller that
ships with EDK is different from the interrupt controller that ships with the
Xilinx ML300 board. If you build your system with EDK you will have to adapt
arch/ppc/kernel/xilinx_pic.c.

Regards,
- Peter


"Kerl, John" wrote:

> Hello all,
>
> There have been some recent posts about Linux & Virtex-II Pro
> (FPGA with PPC405 hard core).  & apparently people have it working.
>
> One question before I start, though:
>
> Of course the kernel starts at *virtual* address 0xc0000000, regardless
> of the processor.  But my understanding is that certain processors have
> zero-based *physical* addresses for RAM, and some don't -- x86 of course
> being an example of the former, and ARM being an example of the latter.
> I believe that PPC is an example of the former.  Certainly our MPC857T
> board, and all the other boards of which I'm aware, have RAM starting at
> physical address 0x00000000.
>
> Now, on our custom Virtex-II Pro board, with Xilinx EDK setup, there's a
> bit (the MSB) in the physical address that specifies whether a memory
> region is on the LMB bus or OPB bus.  We get to pick *which* bit, but
> there must be *a* bit set for the SDRAM.  The upshot is that our SDRAM
> starts at physical address 0xb0000000.  It can't be placed at address 0.
> And block RAM could be made low, but I can't see having megabytes of
> block RAM.
>
> So, I think I have to have the kernel at non-zero physical address
> with PPC405.
>
> Can anyone advise on success or failure of doing so?
>


** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

Re: Low memory on Virtex-II Pro

[Peter 'p2' De Schrijver]

On Fri, Feb 07, 2003 at 02:56:30PM -0700, Kerl, John wrote:
>
> Hello all,
>
> There have been some recent posts about Linux & Virtex-II Pro
> (FPGA with PPC405 hard core).  & apparently people have it working.
>
> One question before I start, though:
>
> Of course the kernel starts at *virtual* address 0xc0000000, regardless
> of the processor.  But my understanding is that certain processors have
> zero-based *physical* addresses for RAM, and some don't -- x86 of course
> being an example of the former, and ARM being an example of the latter.
> I believe that PPC is an example of the former.  Certainly our MPC857T
> board, and all the other boards of which I'm aware, have RAM starting at
> physical address 0x00000000.
>

The 405 has an exception vector pointer register, which is initialized
by linux (linuxppc_2_4_devel cvs tree) with the kernel base. So in
principle it should be possible to have linux run on a system without
memory at address 0. I have never tried this however.

Cheers,

Peter.


** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

Re: Low memory on Virtex-II Pro

[Peter Vandenabeele]

On Fri, Feb 07, 2003 at 02:56:30PM -0700, Kerl, John wrote:
>
> Hello all,
>
> There have been some recent posts about Linux & Virtex-II Pro
> (FPGA with PPC405 hard core). & apparently people have it working

Yes.

> One question before I start, though:
>
> Of course the kernel starts at *virtual* address 0xc0000000, regardless
> of the processor.  But my understanding is that certain processors have
> zero-based *physical* addresses for RAM, and some don't -- x86 of course
> being an example of the former, and ARM being an example of the latter.
> I believe that PPC is an example of the former.  Certainly our MPC857T
> board, and all the other boards of which I'm aware, have RAM starting at
> physical address 0x00000000.
>
> Now, on our custom Virtex-II Pro board, with Xilinx EDK setup, there's a
> bit (the MSB) in the physical address that specifies whether a memory
> region is on the LMB bus or OPB bus.  We get to pick *which* bit, but
> there must be *a* bit set for the SDRAM.  The upshot is that our SDRAM
> starts at physical address 0xb0000000.  It can't be placed at address 0.
> And block RAM could be made low, but I can't see having megabytes of
> block RAM.
>
> So, I think I have to have the kernel at non-zero physical address
> with PPC405.
>
> Can anyone advise on success or failure of doing so?

What is your SDRAM controller ?

When we used the Xilinx SDRAM controller IP (softcore), it was easy
to remap the SDRAM physical base address to 0x00000000 in the .mhs
file (in the Xilinx EDK). We found this to be much less work than trying
to force the Linux kernel to boot from another address than 0x00000000.

Coreconnect PLB bus is what you want to use for off-chip memory
(OPB is low-speed peripherals).

Peter

** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

RE: Low memory on Virtex-II Pro

[Kerl, John]

All:

For anyone who has been breathlessly following this thread:
with Peter's help we now have SDRAM at address 0 on our
Virtex-II Pro board.  Please contact me if you need the
MHS file information.

Thanks Peter.


-----Original Message-----
From: Peter Ryser [mailto:Peter.Ryser@xilinx.com]
Sent: Saturday, February 08, 2003 9:39 PM
To: Kerl John
Cc: 'linuxppc-embedded@lists.linuxppc.org'
Subject: Re: Low memory on Virtex-II Pro


John,

please correct me if I see this wrong but it looks like you are mixing up
MicroBlaze and PowerPC. The LMB is a bus that is only available on
MicroBlaze.
Linux does not have support for MicroBlaze.

However, Linux works great on the PowerPC inside the Virtex-II Pro FPGA when
you map the main memory at address zero. When using EDK to build your system
just set the BASEADDR for the SDRAM to zero.

You might also want to be aware of the fact that the interrupt controller
that
ships with EDK is different from the interrupt controller that ships with
the
Xilinx ML300 board. If you build your system with EDK you will have to adapt
arch/ppc/kernel/xilinx_pic.c.

Regards,
- Peter


"Kerl, John" wrote:

> Hello all,
>
> There have been some recent posts about Linux & Virtex-II Pro
> (FPGA with PPC405 hard core).  & apparently people have it working.
>
> One question before I start, though:
>
> Of course the kernel starts at *virtual* address 0xc0000000, regardless
> of the processor.  But my understanding is that certain processors have
> zero-based *physical* addresses for RAM, and some don't -- x86 of course
> being an example of the former, and ARM being an example of the latter.
> I believe that PPC is an example of the former.  Certainly our MPC857T
> board, and all the other boards of which I'm aware, have RAM starting at
> physical address 0x00000000.
>
> Now, on our custom Virtex-II Pro board, with Xilinx EDK setup, there's a
> bit (the MSB) in the physical address that specifies whether a memory
> region is on the LMB bus or OPB bus.  We get to pick *which* bit, but
> there must be *a* bit set for the SDRAM.  The upshot is that our SDRAM
> starts at physical address 0xb0000000.  It can't be placed at address 0.
> And block RAM could be made low, but I can't see having megabytes of
> block RAM.
>
> So, I think I have to have the kernel at non-zero physical address
> with PPC405.
>
> Can anyone advise on success or failure of doing so?
>

** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/