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* IDE driver support in PPC440
@ 2003-05-14  5:15 Xupei Liang
  2003-05-14  6:56 ` Eugene Surovegin
  0 siblings, 1 reply; 6+ messages in thread
From: Xupei Liang @ 2003-05-14  5:15 UTC (permalink / raw)
  To: linuxppc-embedded; +Cc: tliang


Hi,

I am working on a PPC440 board that supports
a PCI-IDE device, and I am experiencing an
interrupt handling problem.

The PCI-IDE controller uses External Interrupt 7 and
the controller interrupt line is wired to the
processor directly. When the IDE device is
being initialized, I can see that the interrupt
goes off. But the code is stuck in the
ISR and can not get out. Here are the screen
debug messages:

<Linux booting up>
ide1: CMD649 Bus-Master DMA disabled (BIOS)
disabling irq 50 defensively
ppc405_uic_disable - irq 50 word 1 bit 0x12
hda: SanDisk SDCFB-128, ATA DISK drive
ppc405_uic_enable - irq 50 word 1 bit 0x12
ppc405_uic_enable - irq 50 word 1 bit 0x12
ide0 at 0x2000-0x2007,0x3002 on irq 50
hda: 250880 sectors (128 MB) w/1KiB Cache,
CHS=980/8/32
Partition check:
 hda:ppc405_pic_get_irq - irq 50 bit 0x2000
ppc405_uic_disable_and_ack - irq 50 word 1 bit 0x12
ppc405_pic_get_irq - irq 64 bit 0x0
ppc405_pic_get_irq - irq 64 bit 0x0
-------------

I am able to retrieve a stack trace when the
console is displaying the above messages. It is
shown as follows.

-----------
#8  0xc0004950 in do_IRQ (regs=0xc02b68a4) at
irq.c:585
#9  0xc00037cc in ret_from_fork () at entry.S:97
#10 0xc0004730 in ppc_irq_dispatch_handler
(regs=0xc02a522f, irq=3178)
    at irq.c:477
#11 0xc0004938 in do_IRQ (regs=0xc01dbf30) at
irq.c:583
------------

Does anybody have an explaination on what is
going on? Thank you for your help.

Regards,

Terry


** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: IDE driver support in PPC440
  2003-05-14  5:15 Xupei Liang
@ 2003-05-14  6:56 ` Eugene Surovegin
  2003-05-14 15:20   ` Xupei Liang
  0 siblings, 1 reply; 6+ messages in thread
From: Eugene Surovegin @ 2003-05-14  6:56 UTC (permalink / raw)
  To: Xupei Liang; +Cc: linuxppc-embedded


At 10:15 PM 5/13/2003, Xupei Liang wrote:


>I am working on a PPC440 board that supports
>a PCI-IDE device, and I am experiencing an
>interrupt handling problem.
>
>The PCI-IDE controller uses External Interrupt 7 and
>the controller interrupt line is wired to the
>processor directly. When the IDE device is
>being initialized, I can see that the interrupt
>goes off. But the code is stuck in the
>ISR and can not get out. Here are the screen
>debug messages:
>
><Linux booting up>
>ide1: CMD649 Bus-Master DMA disabled (BIOS)
>disabling irq 50 defensively
>ppc405_uic_disable - irq 50 word 1 bit 0x12
>hda: SanDisk SDCFB-128, ATA DISK drive
>ppc405_uic_enable - irq 50 word 1 bit 0x12
>ppc405_uic_enable - irq 50 word 1 bit 0x12
>ide0 at 0x2000-0x2007,0x3002 on irq 50
>hda: 250880 sectors (128 MB) w/1KiB Cache,
>CHS=980/8/32
>Partition check:
>  hda:ppc405_pic_get_irq - irq 50 bit 0x2000
>ppc405_uic_disable_and_ack - irq 50 word 1 bit 0x12
>ppc405_pic_get_irq - irq 64 bit 0x0
>ppc405_pic_get_irq - irq 64 bit 0x0
>-------------

Well, "irq 64" bothers me.
You shouldn't see this message. Real external interrupts are in the range 0-63

Please, check that you are using latest code from 2.4 devel tree
(in particular file arch/ppc/kernel/ppc4xx_pic.c)

BTW, how did you setup trigger and polarity settings for IRQ7 ?

Eugene.


** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: IDE driver support in PPC440
  2003-05-14  6:56 ` Eugene Surovegin
@ 2003-05-14 15:20   ` Xupei Liang
  2003-05-14 16:57     ` Eugene Surovegin
  0 siblings, 1 reply; 6+ messages in thread
From: Xupei Liang @ 2003-05-14 15:20 UTC (permalink / raw)
  To: Eugene Surovegin, linuxppc-embedded


Hi, Eugene,

The IRQ7 is setup as level trigger and active low.

I think what happened is that when the ISR is
serving the first interrupt, which is external
interrupt 7 (number 50), it is interrupted again.
This time, ppc405_pic_get_irq() returns irq 64 because
the routine knows that all interrupts have been
disabled (I have looked at UIC_ER0 and UIC_ER1
and verified that is the case). So the question is,
if all interrupts are disabled, why the code is stuck
inside the ISR?

I am using the lastest 2.4.19 code.

Thank you for your help again.

Regards,

Terry L.


--- Eugene Surovegin <ebs@ebshome.net> wrote:
>
> At 10:15 PM 5/13/2003, Xupei Liang wrote:
>
>
> >I am working on a PPC440 board that supports
> >a PCI-IDE device, and I am experiencing an
> >interrupt handling problem.
> >
> >The PCI-IDE controller uses External Interrupt 7
> and
> >the controller interrupt line is wired to the
> >processor directly. When the IDE device is
> >being initialized, I can see that the interrupt
> >goes off. But the code is stuck in the
> >ISR and can not get out. Here are the screen
> >debug messages:
> >
> ><Linux booting up>
> >ide1: CMD649 Bus-Master DMA disabled (BIOS)
> >disabling irq 50 defensively
> >ppc405_uic_disable - irq 50 word 1 bit 0x12
> >hda: SanDisk SDCFB-128, ATA DISK drive
> >ppc405_uic_enable - irq 50 word 1 bit 0x12
> >ppc405_uic_enable - irq 50 word 1 bit 0x12
> >ide0 at 0x2000-0x2007,0x3002 on irq 50
> >hda: 250880 sectors (128 MB) w/1KiB Cache,
> >CHS=980/8/32
> >Partition check:
> >  hda:ppc405_pic_get_irq - irq 50 bit 0x2000
> >ppc405_uic_disable_and_ack - irq 50 word 1 bit 0x12
> >ppc405_pic_get_irq - irq 64 bit 0x0
> >ppc405_pic_get_irq - irq 64 bit 0x0
> >-------------
>
> Well, "irq 64" bothers me.
> You shouldn't see this message. Real external
> interrupts are in the range 0-63
>
> Please, check that you are using latest code from
> 2.4 devel tree
> (in particular file arch/ppc/kernel/ppc4xx_pic.c)
>
> BTW, how did you setup trigger and polarity settings
> for IRQ7 ?
>
> Eugene.
>
>
>


** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: IDE driver support in PPC440
@ 2003-05-14 16:09 Ralph Blach
  0 siblings, 0 replies; 6+ messages in thread
From: Ralph Blach @ 2003-05-14 16:09 UTC (permalink / raw)
  To: Eugene Surovegin, linuxppc-embedded, Xupei Liang


I am using the MontaVista 2.1 port and the Promise IDE works perfectly.  I just plugged it in and it just ran.

Chip

---------- Original Message ----------------------------------
From: Xupei Liang <tliang@yahoo.com>
Date:  Wed, 14 May 2003 08:20:11 -0700 (PDT)

>
>Hi, Eugene,
>
>The IRQ7 is setup as level trigger and active low.
>
>I think what happened is that when the ISR is
>serving the first interrupt, which is external
>interrupt 7 (number 50), it is interrupted again.
>This time, ppc405_pic_get_irq() returns irq 64 because
>the routine knows that all interrupts have been
>disabled (I have looked at UIC_ER0 and UIC_ER1
>and verified that is the case). So the question is,
>if all interrupts are disabled, why the code is stuck
>inside the ISR?
>
>I am using the lastest 2.4.19 code.
>
>Thank you for your help again.
>
>Regards,
>
>Terry L.
>
>
>--- Eugene Surovegin <ebs@ebshome.net> wrote:
>>
>> At 10:15 PM 5/13/2003, Xupei Liang wrote:
>>
>>
>> >I am working on a PPC440 board that supports
>> >a PCI-IDE device, and I am experiencing an
>> >interrupt handling problem.
>> >
>> >The PCI-IDE controller uses External Interrupt 7
>> and
>> >the controller interrupt line is wired to the
>> >processor directly. When the IDE device is
>> >being initialized, I can see that the interrupt
>> >goes off. But the code is stuck in the
>> >ISR and can not get out. Here are the screen
>> >debug messages:
>> >
>> ><Linux booting up>
>> >ide1: CMD649 Bus-Master DMA disabled (BIOS)
>> >disabling irq 50 defensively
>> >ppc405_uic_disable - irq 50 word 1 bit 0x12
>> >hda: SanDisk SDCFB-128, ATA DISK drive
>> >ppc405_uic_enable - irq 50 word 1 bit 0x12
>> >ppc405_uic_enable - irq 50 word 1 bit 0x12
>> >ide0 at 0x2000-0x2007,0x3002 on irq 50
>> >hda: 250880 sectors (128 MB) w/1KiB Cache,
>> >CHS=980/8/32
>> >Partition check:
>> >  hda:ppc405_pic_get_irq - irq 50 bit 0x2000
>> >ppc405_uic_disable_and_ack - irq 50 word 1 bit 0x12
>> >ppc405_pic_get_irq - irq 64 bit 0x0
>> >ppc405_pic_get_irq - irq 64 bit 0x0
>> >-------------
>>
>> Well, "irq 64" bothers me.
>> You shouldn't see this message. Real external
>> interrupts are in the range 0-63
>>
>> Please, check that you are using latest code from
>> 2.4 devel tree
>> (in particular file arch/ppc/kernel/ppc4xx_pic.c)
>>
>> BTW, how did you setup trigger and polarity settings
>> for IRQ7 ?
>>
>> Eugene.
>>
>>
>>
>
>
>
>

** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: IDE driver support in PPC440
  2003-05-14 15:20   ` Xupei Liang
@ 2003-05-14 16:57     ` Eugene Surovegin
  2003-05-15 14:56       ` Xupei Liang
  0 siblings, 1 reply; 6+ messages in thread
From: Eugene Surovegin @ 2003-05-14 16:57 UTC (permalink / raw)
  To: Xupei Liang; +Cc: linuxppc-embedded


At 08:20 AM 5/14/2003, Xupei Liang wrote:
>Hi, Eugene,
>
>The IRQ7 is setup as level trigger and active low.

<snip>

>This time, ppc405_pic_get_irq() returns irq 64 because
>the routine knows that all interrupts have been
>disabled (I have looked at UIC_ER0 and UIC_ER1
>and verified that is the case).

No, this is not correct, it should return -1.
Otherwise do_IRQ will spin forever (see arch/ppc/kernel/irq.c)

Here is the code in question:

int
ppc405_pic_get_irq(struct pt_regs *regs)
{

        ........

         if (irq == (NR_UIC_IRQS * NR_UICS))
                 irq = -1;

#ifdef UIC_DEBUG
         printk("ppc405_pic_get_irq - irq %d bit 0x%x\n", irq, bits);
#endif

         return (irq);
}


Check, that NR_UIC_IRQS == 32 (defined in include/arch-ppc/irq.h)
and NR_UICS == 2 (defined in /include/arch-ppc/ibm440.h) in your tree.

They weren't set correctly in some early versions of 440GP code.

Eugene


** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: IDE driver support in PPC440
  2003-05-14 16:57     ` Eugene Surovegin
@ 2003-05-15 14:56       ` Xupei Liang
  0 siblings, 0 replies; 6+ messages in thread
From: Xupei Liang @ 2003-05-15 14:56 UTC (permalink / raw)
  To: Eugene Surovegin, linuxppc-embedded


Hi, Eugene,

Thank you for pointing out this. I have updated
ibm440.h and ppc4xx_pic.c as well. Now, in
ppc405_disable_and_ack(), besides acking the
interrupt, it will clear UIC0_UIC1NC bit in the
UIC0_SR register as well. That works for my
board.

Thanks.

Regards,

Terry L.


--- Eugene Surovegin <ebs@ebshome.net> wrote:
>
> At 08:20 AM 5/14/2003, Xupei Liang wrote:
> >Hi, Eugene,
> >
> >The IRQ7 is setup as level trigger and active low.
>
> <snip>
>
> >This time, ppc405_pic_get_irq() returns irq 64
> because
> >the routine knows that all interrupts have been
> >disabled (I have looked at UIC_ER0 and UIC_ER1
> >and verified that is the case).
>
> No, this is not correct, it should return -1.
> Otherwise do_IRQ will spin forever (see
> arch/ppc/kernel/irq.c)
>
> Here is the code in question:
>
> int
> ppc405_pic_get_irq(struct pt_regs *regs)
> {
>
>         ........
>
>          if (irq == (NR_UIC_IRQS * NR_UICS))
>                  irq = -1;
>
> #ifdef UIC_DEBUG
>          printk("ppc405_pic_get_irq - irq %d bit
> 0x%x\n", irq, bits);
> #endif
>
>          return (irq);
> }
>
>
> Check, that NR_UIC_IRQS == 32 (defined in
> include/arch-ppc/irq.h)
> and NR_UICS == 2 (defined in
> /include/arch-ppc/ibm440.h) in your tree.
>
> They weren't set correctly in some early versions of
> 440GP code.
>
> Eugene
>
>
>


** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2003-05-15 14:56 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2003-05-14 16:09 IDE driver support in PPC440 Ralph Blach
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2003-05-14  5:15 Xupei Liang
2003-05-14  6:56 ` Eugene Surovegin
2003-05-14 15:20   ` Xupei Liang
2003-05-14 16:57     ` Eugene Surovegin
2003-05-15 14:56       ` Xupei Liang

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