From: "MERRITT Nigel" <Nigel.Merritt@tenix.com>
To: <linuxppc-embedded@lists.linuxppc.org>
Subject: Interrupts on PPC 405Gr
Date: Fri, 6 Feb 2004 13:47:28 +1100 (EDT) [thread overview]
Message-ID: <200402060247.NAA20760@sprint.tenix.com> (raw)
I am using an IBM PowerPC 405Gr and have been trying to set up IRQ5 as an interrupt. My problem is that the UIC0_ER (interrupt enable) register is not being set by the request_irq call. I have used enable_irq after request_irq but this also has no affect. As this is from a driver, I have even tried setting the correct bit (bit 30 for IRQ 5) directly, by reading UIC0_ER, ORing bit 30 and writing the value back - reading and writing were performed using mfdcr and mtdcr.
I also use mtmsr to set the general interrupt enable bit (EE - bit 16)) in the MSR register.
Does anyone know of other calls that need to be made in order to allow the interrupt enable register to stay set?
Nigel Merritt
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
next reply other threads:[~2004-02-06 2:47 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-02-06 2:47 MERRITT Nigel [this message]
2004-02-06 3:08 ` Interrupts on PPC 405Gr Eugene Surovegin
-- strict thread matches above, loose matches on Subject: below --
2004-02-06 3:37 MERRITT Nigel
2004-02-06 3:52 ` Eugene Surovegin
2004-02-06 6:45 MERRITT Nigel
2004-02-06 6:43 ` Eugene Surovegin
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