* Interrupts on PPC 405Gr
@ 2004-02-06 2:47 MERRITT Nigel
2004-02-06 3:08 ` Eugene Surovegin
0 siblings, 1 reply; 6+ messages in thread
From: MERRITT Nigel @ 2004-02-06 2:47 UTC (permalink / raw)
To: linuxppc-embedded
I am using an IBM PowerPC 405Gr and have been trying to set up IRQ5 as an interrupt. My problem is that the UIC0_ER (interrupt enable) register is not being set by the request_irq call. I have used enable_irq after request_irq but this also has no affect. As this is from a driver, I have even tried setting the correct bit (bit 30 for IRQ 5) directly, by reading UIC0_ER, ORing bit 30 and writing the value back - reading and writing were performed using mfdcr and mtdcr.
I also use mtmsr to set the general interrupt enable bit (EE - bit 16)) in the MSR register.
Does anyone know of other calls that need to be made in order to allow the interrupt enable register to stay set?
Nigel Merritt
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Interrupts on PPC 405Gr
2004-02-06 2:47 MERRITT Nigel
@ 2004-02-06 3:08 ` Eugene Surovegin
0 siblings, 0 replies; 6+ messages in thread
From: Eugene Surovegin @ 2004-02-06 3:08 UTC (permalink / raw)
To: MERRITT Nigel; +Cc: linuxppc-embedded
On Fri, Feb 06, 2004 at 01:47:28PM +1100, MERRITT Nigel wrote:
>
> I am using an IBM PowerPC 405Gr and have been trying to set up IRQ5 as an interrupt.
> My problem is that the UIC0_ER (interrupt enable) register is not being set by the request_irq call.
> Does anyone know of other calls that need to be made in order to allow the interrupt enable register to stay set?
> I have used enable_irq after request_irq but this also has no affect. As this is from a driver,
> I have even tried setting the correct bit (bit 30 for IRQ 5) directly, by reading UIC0_ER, ORing
> bit 30 and writing the value back - reading and writing were performed using mfdcr and mtdcr.
> I also use mtmsr to set the general interrupt enable bit (EE - bit 16)) in the MSR register.
>
Please, don't touch MSR and UIC registers. request_irq should work
just fine (I never had problems with UIC on 405 boards).
Probably you are doing something completely wrong.
Some questions:
1) What kernel tree are you using?
2) Are you sure IRQ5 is actually _generated_ by your external device?
Did you use scope to verify this?
3) Are you sure IRQ5 is enabled in CPC0_CR0 register and not used as
GPIO? Are the polarity and trigger settings are correct for your
external device?
Please, provide more detailed info (with all registers values and/or
code samples) if you wanted somebody to help you.
Eugene.
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: Interrupts on PPC 405Gr
@ 2004-02-06 3:37 MERRITT Nigel
2004-02-06 3:52 ` Eugene Surovegin
0 siblings, 1 reply; 6+ messages in thread
From: MERRITT Nigel @ 2004-02-06 3:37 UTC (permalink / raw)
To: Eugene Surovegin; +Cc: linuxppc-embedded
The kernel is 2.4.18 from Timesys.
We have a logic analyser hooked up so we know for certain that the
signal is being generated on the correct line and is entering the UIC.
CPC0_CR0 is being set using the (probably very wrong) code:
register_val = mfdcr(CPC0_CR0); // Read value from the register.
// Set to 0.
register_val = register_val & MASK_BIT_NOT_6;
register_val = register_val & MASK_BIT_NOT_7;
register_val = register_val & MASK_BIT_NOT_16;
register_val = register_val & MASK_BIT_NOT_17;
register_val = register_val & MASK_BIT_NOT_18;
// Set to 1.
register_val = register_val | MASK_BIT_9;
register_val = register_val | MASK_BIT_10;
register_val = register_val | MASK_BIT_12;
register_val = register_val | MASK_BIT_13;
// Write the value back to the register.
mtdcr(CPC0_CR0, register_val);
Please tell me the correct way to set these registers, as I can't find
the functions to call in our documentation.
Polarity and trigger settings are being set in a similar manner, i.e:
// Write the value back to the register.
mtdcr(CPC0_CR0, register_val);
//////////////////////////////////////
// Set the interrupts to falling edge.
//////////////////////////////////////
register_val = mfdcr(UIC0_TR);
register_val = register_val | MASK_BIT_24;
register_val = register_val | MASK_BIT_30;
register_val = register_val | MASK_BIT_31;
mtdcr(UIC0_TR, register_val);
Again, how do these get set if not by adjusting the registers?
The GPIO lines are set up as follows:
reg = (unsigned int*)GPIO0_TCR;
register_val = *reg;
register_val = register_val | MASK_BIT_14;
register_val = register_val | MASK_BIT_17;
*reg = register_val;
The request_irq call is:
res = request_irq(5, DataReadyInterrupt,
SA_INTERRUPT, "fpga_o", reg_handle_o);
..with the handler being:
void DataReadyInterrupt(int par1, void *par2, struct pt_regs *par3)
Many thanks,
Nigel
-----Original Message-----
From: Eugene Surovegin [mailto:ebs@ebshome.net]
Sent: Friday, 6 February 2004 1:38 PM
To: MERRITT Nigel
Cc: linuxppc-embedded@lists.linuxppc.org
Subject: Re: Interrupts on PPC 405Gr
On Fri, Feb 06, 2004 at 01:47:28PM +1100, MERRITT Nigel wrote:
>
> I am using an IBM PowerPC 405Gr and have been trying to set up IRQ5 as
an interrupt.
> My problem is that the UIC0_ER (interrupt enable) register is not
being set by the request_irq call.
> Does anyone know of other calls that need to be made in order to allow
the interrupt enable register to stay set?
> I have used enable_irq after request_irq but this also has no affect.
As this is from a driver,
> I have even tried setting the correct bit (bit 30 for IRQ 5) directly,
by reading UIC0_ER, ORing
> bit 30 and writing the value back - reading and writing were performed
using mfdcr and mtdcr.
> I also use mtmsr to set the general interrupt enable bit (EE - bit
16)) in the MSR register.
>
Please, don't touch MSR and UIC registers. request_irq should work
just fine (I never had problems with UIC on 405 boards).
Probably you are doing something completely wrong.
Some questions:
1) What kernel tree are you using?
2) Are you sure IRQ5 is actually _generated_ by your external device?
Did you use scope to verify this?
3) Are you sure IRQ5 is enabled in CPC0_CR0 register and not used as
GPIO? Are the polarity and trigger settings are correct for your
external device?
Please, provide more detailed info (with all registers values and/or
code samples) if you wanted somebody to help you.
Eugene.
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Interrupts on PPC 405Gr
2004-02-06 3:37 Interrupts on PPC 405Gr MERRITT Nigel
@ 2004-02-06 3:52 ` Eugene Surovegin
0 siblings, 0 replies; 6+ messages in thread
From: Eugene Surovegin @ 2004-02-06 3:52 UTC (permalink / raw)
To: MERRITT Nigel; +Cc: linuxppc-embedded
On Fri, Feb 06, 2004 at 02:37:18PM +1100, MERRITT Nigel wrote:
>
> The kernel is 2.4.18 from Timesys.
Well, maybe you should ask them? I wasn't able to find any
downloadable PPC 4xx BSPs on Timesys web site.
> We have a logic analyser hooked up so we know for certain that the
> signal is being generated on the correct line and is entering the UIC.
OK
> CPC0_CR0 is being set using the (probably very wrong) code:
>
> register_val = mfdcr(CPC0_CR0); // Read value from the register.
>
> // Set to 0.
> register_val = register_val & MASK_BIT_NOT_6;
> register_val = register_val & MASK_BIT_NOT_7;
[snip]
I'd prefer real (hex) values, even better, just print them out after
you set them, i.e.
printk("0x%08x\n", mfcdr(CPC0_CR0));
I have no idea how you defined all these macros.
> Polarity and trigger settings are being set in a similar manner, i.e:
[snip]
> Again, how do these get set if not by adjusting the registers?
Well, official PPC kernels have a sane way to do this, look for
ibm4xxPIC_InitSenses in arch/ppc/platforms. Not sure whether Timesys
kernel has it.
And this kind of stuff (e.g. CPC0_CR0, polarity/trigerring settings)
is usually done in firmware not in the kernel.
Try official PPC kernel trees, at least they are known to work on
405 hardware. Maybe you problems are Timesys kernel specific.
Eugene.
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Interrupts on PPC 405Gr
2004-02-06 6:45 MERRITT Nigel
@ 2004-02-06 6:43 ` Eugene Surovegin
0 siblings, 0 replies; 6+ messages in thread
From: Eugene Surovegin @ 2004-02-06 6:43 UTC (permalink / raw)
To: MERRITT Nigel; +Cc: linuxppc-embedded
On Fri, Feb 06, 2004 at 05:45:17PM +1100, MERRITT Nigel wrote:
> When calling request_irq, the irq number had to be 30, which is the bit
> in the UIC0_ER register that needs setting. I was passing it 5, which
> is the IRQ I wanted setting. When I changed the IRQ number to 30 it
> worked! I'm not sure if this is a screw up on my part for not passing
> the correct value in the first place, or an error in the Timesys kernel
> (surely the number passed in should be the IRQ required, not the bit
> position in the UIC registers).
It's your error, just think what you have to pass to request_irq if
you want to hook UART0 interrupt...
IRQ5 - is _external_ (to the chip) interrupt line and NOT an interrupt
number. _All_ UIC interrupts are external to the core (but not
all of them are IRQx lines).
Eugene.
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: Interrupts on PPC 405Gr
@ 2004-02-06 6:45 MERRITT Nigel
2004-02-06 6:43 ` Eugene Surovegin
0 siblings, 1 reply; 6+ messages in thread
From: MERRITT Nigel @ 2004-02-06 6:45 UTC (permalink / raw)
To: Eugene Surovegin; +Cc: linuxppc-embedded
Solved it. For your information...
When calling request_irq, the irq number had to be 30, which is the bit
in the UIC0_ER register that needs setting. I was passing it 5, which
is the IRQ I wanted setting. When I changed the IRQ number to 30 it
worked! I'm not sure if this is a screw up on my part for not passing
the correct value in the first place, or an error in the Timesys kernel
(surely the number passed in should be the IRQ required, not the bit
position in the UIC registers).
Nigel
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
^ permalink raw reply [flat|nested] 6+ messages in thread
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