From: Tom Rini <trini@kernel.crashing.org>
To: Adrian Cox <adrian@humboldt.co.uk>
Cc: linuxppc-embedded@lists.linuxppc.org
Subject: Re: Caching in the MPC107, linux 2.6
Date: Mon, 15 Mar 2004 13:38:49 -0700 [thread overview]
Message-ID: <20040315203849.GA13167@smtp.west.cox.net> (raw)
In-Reply-To: <1079380996.1677.2.camel@newt>
On Mon, Mar 15, 2004 at 08:03:16PM +0000, Adrian Cox wrote:
> On Sat, 2004-03-13 at 17:07, Tom Rini wrote:
>
> > Instead do:
> > BEGIN_FTR_SECTION
> > ori r8,r8,_PAGE_COHERENT
> > END_FTR_SECTION_IFSET(CPU_FTR_745X_MPC107)
> >
> > And have the code that sets SPEC7450 also check for an MPC107.
>
> Something like this?
Actually, I was thinking that having an extra nop there on the !SMP &&
!(745x && MPC107) case wouldn't hurt much / at all, and having this
feature bit be done unconditionally. But in cpu_setup_6xx.S we would
compare the host bridge vendor / device ID to that of an mpc107. Or am
I not thinking right, and doing that comparison at that time would be a
bad idea? If so, I can live with it being an unconditional option, iff
it's only required when MPC10X_STORE_GATHERING is enabled.
--
Tom Rini
http://gate.crashing.org/~trini/
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
next prev parent reply other threads:[~2004-03-15 20:38 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-03-12 10:46 Caching in the MPC107, linux 2.6 Adrian Cox
2004-03-12 22:32 ` Tom Rini
2004-03-13 11:32 ` Adrian Cox
2004-03-13 17:07 ` Tom Rini
2004-03-15 20:03 ` Adrian Cox
2004-03-15 20:38 ` Tom Rini [this message]
2004-03-15 22:42 ` Adrian Cox
2004-03-15 22:48 ` Tom Rini
2004-03-16 18:06 ` Adrian Cox
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