From mboxrd@z Thu Jan 1 00:00:00 1970 Date: Wed, 24 Mar 2004 09:05:28 -0700 From: Matt Porter To: Neil Wilson Cc: Eugene Surovegin , linuxppc-embedded@lists.linuxppc.org Subject: Re: IBM 440GX, Ocotea... Message-ID: <20040324090528.A14405@home.com> References: <3506EDCDEC47904CBE6FD2E1DEEA8984020CF985@fs5.airspan.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii In-Reply-To: <3506EDCDEC47904CBE6FD2E1DEEA8984020CF985@fs5.airspan.com>; from NWilson@Airspan.com on Wed, Mar 24, 2004 at 02:21:38PM -0000 Sender: owner-linuxppc-embedded@lists.linuxppc.org List-Id: On Wed, Mar 24, 2004 at 02:21:38PM -0000, Neil Wilson wrote: > > > > Does this mean that the L2 cache is unusable on current > > revisions of > > > the chip? [That's why we would like to use this chip.] > > > > Yes, we found problems with current chip revisions (A & B). > > Ask your IBM contact for more information. > > > > Can you elaborate a bit on this please ?, we are considering using this > processor but would need the cache. > I have had a quick look at the 2 errata docs I found on the IBM web > site but must be missing the bit this relate to. I know if I elaborated the "issue" it would violate the NDA that we (my employer) are covered under. I assume Eugene is in a similar position. You really should talk to IBM, that's what mvista is forced to tell its 440GX customers. :) -Matt ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/