From: Matt Porter <mporter@kernel.crashing.org>
To: akpm@osdl.org
Cc: linux-kernel@vger.kernel.org, linuxppc-embedded@ozlabs.org
Subject: [PATCH][PPC32] Disable broken L2 cache on all 440GX revs
Date: Tue, 26 Oct 2004 13:58:47 -0700 [thread overview]
Message-ID: <20041026135847.A16409@home.com> (raw)
Always disable L2 cache on PPC440GX. All revs/speeds of silicon
have parity error problems despite errata claims to the contrary.
Signed-off-by: Matt Porter <mporter@kernel.crashing.org>
===== arch/ppc/platforms/4xx/ocotea.c 1.8 vs edited =====
--- 1.8/arch/ppc/platforms/4xx/ocotea.c 2004-10-18 22:26:41 -07:00
+++ edited/arch/ppc/platforms/4xx/ocotea.c 2004-10-26 13:40:44 -07:00
@@ -350,8 +350,12 @@
ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
ocp_sys_info.opb_bus_freq = clocks.opb;
- /* Disable L2-Cache on broken hardware, enable it otherwise */
- ibm440gx_l2c_setup(&clocks);
+ /*
+ * Always disable L2 cache. All revs/speeds of silicon
+ * have parity error problems despite errata claims to
+ * the contrary.
+ */
+ ibm440gx_l2c_disable();
ibm44x_platform_init();
next reply other threads:[~2004-10-26 20:58 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-10-26 20:58 Matt Porter [this message]
2004-10-27 13:20 ` [PATCH][PPC32] Disable broken L2 cache on all 440GX revs Gerhard Jaeger
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