* [PATCH][PPC32] Disable broken L2 cache on all 440GX revs
@ 2004-10-26 20:58 Matt Porter
2004-10-27 13:20 ` Gerhard Jaeger
0 siblings, 1 reply; 2+ messages in thread
From: Matt Porter @ 2004-10-26 20:58 UTC (permalink / raw)
To: akpm; +Cc: linux-kernel, linuxppc-embedded
Always disable L2 cache on PPC440GX. All revs/speeds of silicon
have parity error problems despite errata claims to the contrary.
Signed-off-by: Matt Porter <mporter@kernel.crashing.org>
===== arch/ppc/platforms/4xx/ocotea.c 1.8 vs edited =====
--- 1.8/arch/ppc/platforms/4xx/ocotea.c 2004-10-18 22:26:41 -07:00
+++ edited/arch/ppc/platforms/4xx/ocotea.c 2004-10-26 13:40:44 -07:00
@@ -350,8 +350,12 @@
ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
ocp_sys_info.opb_bus_freq = clocks.opb;
- /* Disable L2-Cache on broken hardware, enable it otherwise */
- ibm440gx_l2c_setup(&clocks);
+ /*
+ * Always disable L2 cache. All revs/speeds of silicon
+ * have parity error problems despite errata claims to
+ * the contrary.
+ */
+ ibm440gx_l2c_disable();
ibm44x_platform_init();
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH][PPC32] Disable broken L2 cache on all 440GX revs
2004-10-26 20:58 [PATCH][PPC32] Disable broken L2 cache on all 440GX revs Matt Porter
@ 2004-10-27 13:20 ` Gerhard Jaeger
0 siblings, 0 replies; 2+ messages in thread
From: Gerhard Jaeger @ 2004-10-27 13:20 UTC (permalink / raw)
To: Matt Porter; +Cc: linuxppc-embedded
On Dienstag 26 Oktober 2004 22:58, Matt Porter wrote:
> Always disable L2 cache on PPC440GX. All revs/speeds of silicon
> have parity error problems despite errata claims to the contrary.
> Signed-off-by: Matt Porter <mporter@kernel.crashing.org>
Hi Matt,
is there any test, with which you can reproduce these failures?
We have here custom boards based on the 440GX latest rev and
we need to use them with enabled L2 cache...
TIA,
Gerhard
^ permalink raw reply [flat|nested] 2+ messages in thread
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