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From: Gerhard Jaeger <gjaeger@sysgo.com>
To: Matt Porter <mporter@kernel.crashing.org>
Date: Wed, 27 Oct 2004 15:20:51 +0200
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Cc: linuxppc-embedded@ozlabs.org
Subject: Re: [PATCH][PPC32] Disable broken L2 cache on all 440GX revs
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On Dienstag 26 Oktober 2004 22:58, Matt Porter wrote:
> Always disable L2 cache on PPC440GX. All revs/speeds of silicon
> have parity error problems despite errata claims to the contrary.
> Signed-off-by: Matt Porter <mporter@kernel.crashing.org>

Hi Matt,

is there any test, with which you can reproduce these failures?
We have here custom boards based on the 440GX latest rev and 
we need to use them with enabled L2 cache...

TIA,
  Gerhard