From: Matt Porter <mporter@kernel.crashing.org>
To: Kumar Gala <kumar.gala@freescale.com>
Cc: "Barbier, Renaud \(GE Infrastructure\)" <Renaud.Barbier@ge.com>,
linuxppc-embedded@ozlabs.org
Subject: Re: 440GX MMU
Date: Mon, 6 Dec 2004 13:15:00 -0700 [thread overview]
Message-ID: <20041206131500.A9960@home.com> (raw)
In-Reply-To: <35B36824-47B6-11D9-8BFE-000393DBC2E8@freescale.com>; from kumar.gala@freescale.com on Mon, Dec 06, 2004 at 12:39:49PM -0600
On Mon, Dec 06, 2004 at 12:39:49PM -0600, Kumar Gala wrote:
> The TS provides an additional bit of address space on Book-E processors
> (440, e500, etc). An exception automatically clears the MSR[IS, DS]
> fields which are used to compare against the TLB's TS field.
>
> It was the case at one point in time (may still be) that on 440, the
> interrupt context was TS = 0, everything else was TS = 1. Matt was
> going to (or may have) changed it so everything is TS = 0 so we could
> save a few TLB entries.
It's changed in 2.6 (all AS=0), in 2.4 I never got around to finishing
the update to the MMU handling. Since then, 2.6 has gone way beyond
2.4 in features/fixes so I don't intend to do anything more with
2.4. Patches are welcome for linuxppc-2.4, though.
-Matt
prev parent reply other threads:[~2004-12-06 20:15 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-12-06 18:23 440GX MMU Barbier, Renaud (GE Infrastructure)
2004-12-06 18:39 ` Kumar Gala
2004-12-06 20:15 ` Matt Porter [this message]
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