SMC/SCC uart problem with MPC852T

SMC/SCC uart problem with MPC852T

[David Jander]

Hi,

I have been searching for a way to do the BRG routing to SCC3 and SCC4 on the 
MPC852T, so that BGR3 is routed to SCC3 and SMC1 and BRG4 to SCC4. I could 
not find anything in the kernel (CVS linux_2_4_devel from DENX) to do this.
I think I also need a special ucode-patch, but I don't know where to look for 
it either.
Right now SMC1 works as serial console (115200 baud).
The kernel says this:
...
CPM UART driver version 0.04
ttyS0 at 0x0280 is on SMC1 using BRG1
ttyS1 at 0x0200 is on SCC3 using BRG2
ttyS2 at 0x0300 is on SCC4 using BRG3
...
IMHO this can't be right. At least not for the MPC852T.
If I connect a device to ttyS1 or ttyS2, it seems to work OK though, but if I 
connect the respective RX pin directly to the corresponding TX pin, strange 
things begin to happen. /proc/interrupt counts skyrocket, and I get a lot of 
repeated data back from the serial port. It looks like as if CPM buffers 
overlap or something like that.

Searching on Google I was able to find these boot-messages from someone using 
an MPC852T:

....
CPM UART driver version 0.03
ttyS0 at 0x0280 is on SMC1 using BRG3 - SMC1/SCC3/I2C/SPI Patch enabled
ttyS1 at 0x0200 is on SCC3 using BRG3
ttyS2 at 0x0300 is on SCC4 using BRG4
....

That looks a lot better, but I wonder how he accomplished this? What's that 
"SMC1/SCC3/I2C/SPI Patch" ? Where do I get it from?

Greetings,

-- 
David Jander
Protonic Holland.

Re: SMC/SCC uart problem with MPC852T

[Dan Malek]

On Dec 30, 2004, at 6:46 AM, David Jander wrote:

> I have been searching for a way to do the BRG routing to SCC3 and SCC4 
> on the
> MPC852T, so that BGR3 is routed to SCC3 and SMC1 and BRG4 to SCC4. I 
> could
> not find anything in the kernel (CVS linux_2_4_devel from DENX) to do 
> this.

There isn't anything exactly to do this.  If you get the linuxppc-2.4 
from BK,
there is an updated uart.c driver that will help with this.  All of the 
BRG
management is handled by a single function, and you can modify this
accordingly to meet your requirements.


> Searching on Google I was able to find these boot-messages from 
> someone using
> an MPC852T:

Must have been a locally customized driver.


	-- Dan

MPC5200 PCI byte-swapping

[Mark Chambers]

I've just realized that the 5200 does byte-lane swapping
on all PCI accesses.  That is, if you write a 32 bit word
0x12345678, 0x12 will go out on byte 0, 0x34 on byte 1,
etc.  Unfortunately, my target, a T.I. DM642, does not
do this, so I've got a big/little endian mismatch.  A couple
of questions if anybody knows:

- Do all MPC8xxx processors do this - byte swap on
all PCI accesses, not just configuration space?

- Is there an elegant (simple) way to re-swap the bytes?
It's not a big problem really, but if there were a way to 
set LE mode on a particular page or something like that
it might be worth it.

Thanks,
Mark Chambers

Re: MPC5200 PCI byte-swapping

[Sylvain Munaut]

Mark Chambers wrote:

>I've just realized that the 5200 does byte-lane swapping
>on all PCI accesses.  That is, if you write a 32 bit word
>0x12345678, 0x12 will go out on byte 0, 0x34 on byte 1,
>etc.  Unfortunately, my target, a T.I. DM642, does not
>do this, so I've got a big/little endian mismatch.  A couple
>of questions if anybody knows:
>
>- Do all MPC8xxx processors do this - byte swap on
>all PCI accesses, not just configuration space?
>
>- Is there an elegant (simple) way to re-swap the bytes?
>It's not a big problem really, but if there were a way to 
>set LE mode on a particular page or something like that
>it might be worth it.
>
>  
>
I'm not sure of what you mean but look at the mapping
aroung pdf page 337 of the user manual. It's not configurable
as far as I can see.


    Sylvain

Re: MPC5200 PCI byte-swapping

[Mark Chambers]

> Mark Chambers wrote:
> 
> >I've just realized that the 5200 does byte-lane swapping
> >on all PCI accesses.  That is, if you write a 32 bit word
> >0x12345678, 0x12 will go out on byte 0, 0x34 on byte 1,
> >etc.  Unfortunately, my target, a T.I. DM642, does not
> >do this, so I've got a big/little endian mismatch.  A couple
> >of questions if anybody knows:
> >
Sylvain wrote:

> I'm not sure of what you mean but look at the mapping
> aroung pdf page 337 of the user manual. It's not configurable
> as far as I can see.
> 

Thanks.  I had an older manual that didn't spell it out so
clearly.

I've been trying to interpret the PCI sections for some other
82xx family parts, and it appears that they do NOT do this
byte lane swapping, so this make the 5200 non-standard in
this regard, which is unfortunate.  If I'm understanding this
right, one would have to have different drivers for a PCI
device on a 5200 and an 8270, for instance.

Also, I note that when doing simple block reads from pre-
fetchable PCI space, it appears the 5200 does not prefetch,
but does each read individually.  This is using stock ELDK
u-boot and 2.4.24 so I haven't yet determined if it's a
configuration matter, (or ruled out target disconnects)
but I'm suspecting that you can't get burst mode from the 
5200 without using DMA.

Mark Chambers

Re: MPC5200 PCI byte-swapping

[Sylvain Munaut]

>Thanks.  I had an older manual that didn't spell it out so
>clearly.
>
>I've been trying to interpret the PCI sections for some other
>82xx family parts, and it appears that they do NOT do this
>byte lane swapping, so this make the 5200 non-standard in
>this regard, which is unfortunate.  If I'm understanding this
>right, one would have to have different drivers for a PCI
>device on a 5200 and an 8270, for instance.
>  
>
Mmmm ...
Still I use the intel eepro driver without problems or modifications.
As long as the driver uses the proper readl/writel that should do
it or am I mistaken ?

I have a FPGA mounted with pci interface, I'll try to see what happens on
the bus

>Also, I note that when doing simple block reads from pre-
>fetchable PCI space, it appears the 5200 does not prefetch,
>but does each read individually.  This is using stock ELDK
>u-boot and 2.4.24 so I haven't yet determined if it's a
>configuration matter, (or ruled out target disconnects)
>but I'm suspecting that you can't get burst mode from the 
>5200 without using DMA.
>  
>
Last time I checked, the 2.4 from denx didn't create a pci
window for prefetchable memory so prefetch mem zone
were mapped as non-prefetchable, so no burst for sure.



Sylvain

Re: MPC5200 PCI byte-swapping

[Stefan Nickl]

On Mon, 2005-01-03 at 17:47 +0100, Sylvain Munaut wrote:
> >Thanks.  I had an older manual that didn't spell it out so
> >clearly.
> >
> >I've been trying to interpret the PCI sections for some other
> >82xx family parts, and it appears that they do NOT do this
> >byte lane swapping, so this make the 5200 non-standard in
> >this regard, which is unfortunate.  If I'm understanding this
> >right, one would have to have different drivers for a PCI
> >device on a 5200 and an 8270, for instance.
> >  
> >
> Mmmm ...
> Still I use the intel eepro driver without problems or modifications.
> As long as the driver uses the proper readl/writel that should do
> it or am I mistaken ?

This reminds me of an issue with the Coral P PCI graphics chip I
encountered a while ago. The driver is from the Denx CVS and was
apparently developed on a 5200.

When I tried it on a mpc8540, the console text looked blueish, but I
could not investigate further. But I know where I'd look at now ...

-- 
Stefan Nickl
Kontron Modular Computers

SMC/SCC uart problem with MPC852T

[David Jander]

Hi,

I have been searching for a way to do the BRG routing to SCC3 and SCC4 on the 
MPC852T, so that BGR3 is routed to SCC3 and SMC1 and BRG4 to SCC4. I could 
not find anything in the kernel (CVS linux_2_4_devel from DENX) to do this.
I think I also need a special ucode-patch, but I don't know where to look for 
it either.
Right now SMC1 works as serial console (115200 baud).
The kernel says this:
...
CPM UART driver version 0.04
ttyS0 at 0x0280 is on SMC1 using BRG1
ttyS1 at 0x0200 is on SCC3 using BRG2
ttyS2 at 0x0300 is on SCC4 using BRG3
...
IMHO this can't be right. At least not for the MPC852T.
If I connect a device to ttyS1 or ttyS2, it seems to work OK though, but if I 
connect the respective RX pin directly to the corresponding TX pin, strange 
things begin to happen. /proc/interrupt counts skyrocket, and I get a lot of 
repeated data back from the serial port. It looks like as if CPM buffers 
overlap or something like that.

Searching on Google I was able to find these boot-messages from someone using 
an MPC852T:

....
CPM UART driver version 0.03
ttyS0 at 0x0280 is on SMC1 using BRG3 - SMC1/SCC3/I2C/SPI Patch enabled
ttyS1 at 0x0200 is on SCC3 using BRG3
ttyS2 at 0x0300 is on SCC4 using BRG4
....

That looks a lot better, but I wonder how he accomplished this? What's that 
"SMC1/SCC3/I2C/SPI Patch" ? Where do I get it from?

Greetings,

-- 
David Jander
Protonic Holland.