[PATCH] ppc32: ppc4xx_pic - add acknowledge when enabling level-sensitive IRQ

[PATCH] ppc32: ppc4xx_pic - add acknowledge when enabling level-sensitive IRQ

[Eugene Surovegin]

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Andrew,

this patch adds interrupt acknowledge to the PPC4xx PIC enable_irq 
implementation for level-sensitive IRQ sources. This helps in cases 
when enable/disable_irq is used in interrupt handlers for hardware, 
which requires IRQ acknowledge to be issued from non-interrupt context 
(e.g. when actual ACK in device needs an I2C transaction). For such 
strange hardware, interrupt handler disables IRQ and defers actual ACK 
to some other context. When this happens, IRQ is enabled again. For 
level-sensitive sources we get spurious triggering right after IRQ 
is enabled. This patch fixes this.
Suggested by Tolunay Orkun <listmember@orkun.us>.

Signed-off-by: Eugene Surovegin <ebs@ebshome.net>

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===== arch/ppc/syslib/ppc4xx_pic.c 1.15 vs edited =====
--- 1.15/arch/ppc/syslib/ppc4xx_pic.c	2005-03-04 22:41:17 -08:00
+++ edited/arch/ppc/syslib/ppc4xx_pic.c	2005-04-03 12:00:55 -07:00
@@ -41,7 +41,10 @@
 #define UIC_HANDLERS(n)							\
 static void ppc4xx_uic##n##_enable(unsigned int irq)			\
 {									\
-	ppc_cached_irq_mask[n] |= IRQ_MASK_UIC##n(irq);			\
+	u32 mask = IRQ_MASK_UIC##n(irq);				\
+	if (irq_desc[irq].status & IRQ_LEVEL)				\
+		mtdcr(DCRN_UIC_SR(UIC##n), mask);			\
+	ppc_cached_irq_mask[n] |= mask;					\
 	mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]);		\
 }									\
 									\