From: Eugene Surovegin <ebs@ebshome.net>
To: Sanjay Bajaj <sbajaj@tsi-telsys.com>
Cc: linuxppc-embedded@ozlabs.org
Subject: Re: tah reset?
Date: Thu, 19 May 2005 11:23:11 -0700 [thread overview]
Message-ID: <20050519182311.GA27236@gate.ebshome.net> (raw)
In-Reply-To: <0007F077BB3476449151699150E8FEA21A7B9D@exchange.tsi-telsys.com>
On Thu, May 19, 2005 at 02:14:20PM -0400, Sanjay Bajaj wrote:
> While trying to reset the TAH on emac2 of PPC440GX, the Soft Reset
> (SR) bit never resets itself to 0. Does anybody know the reason for
> it?
Did you enable TAH0 in SDR0_MFR register?
Also, I don't remember for sure, but TAH may have the same problem as
EMAC, namely, it won't go out of reset if there is no RX clock from
PHY.
--
Eugene
next prev parent reply other threads:[~2005-05-19 18:23 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-05-19 18:14 tah reset? Sanjay Bajaj
2005-05-19 18:23 ` Eugene Surovegin [this message]
-- strict thread matches above, loose matches on Subject: below --
2005-05-19 19:45 Sanjay Bajaj
2005-05-19 20:13 ` Eugene Surovegin
2005-05-23 19:17 Sanjay Bajaj
2005-05-23 20:04 ` Eugene Surovegin
2005-05-23 20:56 Sanjay Bajaj
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