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Date: Thu, 19 May 2005 11:23:11 -0700
From: Eugene Surovegin <ebs@ebshome.net>
To: Sanjay Bajaj <sbajaj@tsi-telsys.com>
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Cc: linuxppc-embedded@ozlabs.org
Subject: Re: tah reset?
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On Thu, May 19, 2005 at 02:14:20PM -0400, Sanjay Bajaj wrote:
> While trying to reset the TAH on emac2 of PPC440GX, the Soft Reset 
> (SR) bit never resets itself to 0. Does anybody know the reason for 
> it?

Did you enable TAH0 in SDR0_MFR register?

Also, I don't remember for sure, but TAH may have the same problem as 
EMAC, namely, it won't go out of reset if there is no RX clock from 
PHY.

-- 
Eugene