From: Eugene Surovegin <ebs@ebshome.net>
To: Sanjay Bajaj <sbajaj@tsi-telsys.com>
Cc: linuxppc-embedded@ozlabs.org
Subject: Re: tah reset?
Date: Thu, 19 May 2005 13:13:29 -0700 [thread overview]
Message-ID: <20050519201329.GB27236@gate.ebshome.net> (raw)
In-Reply-To: <0007F077BB3476449151699150E8FEA21A7B9E@exchange.tsi-telsys.com>
On Thu, May 19, 2005 at 03:45:50PM -0400, Sanjay Bajaj wrote:
> Eugene,
>
> Yes, TAH0 in SDR0_MFR register is enabled.
>
> EMAC is able to reset correctly, but TAH isn't at the same location
> [in emac_probe()]. PHY is connected to EMAC and TAH is behind EMAC.
> I do not understand how the RX clock from PHY will reach TAH? Any suggestions ?
E.g. TAH RX path is clocked from the same source as EMAC, I think
it's quite obvious, but I digress.
What are you doing? Having problems with EMAC driver? What kernel
version? What board?
You can try my new NAPI EMAC driver (http://kernel.ebshome.net/).
--
Eugene
next prev parent reply other threads:[~2005-05-19 20:13 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-05-19 19:45 tah reset? Sanjay Bajaj
2005-05-19 20:13 ` Eugene Surovegin [this message]
-- strict thread matches above, loose matches on Subject: below --
2005-05-23 20:56 Sanjay Bajaj
2005-05-23 19:17 Sanjay Bajaj
2005-05-23 20:04 ` Eugene Surovegin
2005-05-19 18:14 Sanjay Bajaj
2005-05-19 18:23 ` Eugene Surovegin
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