RE: tah reset?

RE: tah reset?

[Sanjay Bajaj]

FYI,

I did find the source of the reset tah issue. The physical address of =
TAH 0 and TAH 1 was ending in B00h and D00h respectively. But in the UM, =
it ends in B50 and D50. the file affected is ibm440gx.c in =
arch/ppc/platforms.

Thanks,
Sanjay

-----Original Message-----
From: Eugene Surovegin [mailto:ebs@ebshome.net]
Sent: Thursday, May 19, 2005 2:23 PM
To: Sanjay Bajaj
Cc: linuxppc-embedded@ozlabs.org
Subject: Re: tah reset?


On Thu, May 19, 2005 at 02:14:20PM -0400, Sanjay Bajaj wrote:
> While trying to reset the TAH on emac2 of PPC440GX, the Soft Reset=20
> (SR) bit never resets itself to 0. Does anybody know the reason for=20
> it?

Did you enable TAH0 in SDR0_MFR register?

Also, I don't remember for sure, but TAH may have the same problem as=20
EMAC, namely, it won't go out of reset if there is no RX clock from=20
PHY.

--=20
Eugene

Re: tah reset?

[Eugene Surovegin]

On Mon, May 23, 2005 at 03:17:26PM -0400, Sanjay Bajaj wrote:
> I did find the source of the reset tah issue. The physical address 
> of TAH 0 and TAH 1 was ending in B00h and D00h respectively. But in 
> the UM, it ends in B50 and D50. the file affected is ibm440gx.c in 
> arch/ppc/platforms.

Linux 2.6 has correct values for TAH base address, 2.4 doesn't have 
any support for TAH at all.

Where did you get this incorrect code?

You see, you should have used supported sources (2.6) or the one I 
recommended to you (my 2.4 backport) but you have ignored this  
suggestion and wasted your time and time of people on this mail list.

Please, next time if you use some stuff which isn't in kernel.org's 
tree, direct you questions to the person who made those patches, 
because we cannot help you as we don't have the source code you are 
using.

-- 
Eugene

RE: tah reset?

[Sanjay Bajaj]

My intention is not to waste anybody's time and I think, I did not. As I =
mentioned to you earlier that I am working on the vendor provided =
version of Linux Kernel 2.4.27-pre3, which looks clearly from =
kernel.org. The value of PPC440GX_TAH0_ADDR and PPC440GX_TAH1_ADDR in =
arch/ppc/platforms/ibm440gx.h is 0x0000000140000b00 & 0x0000000140000d00 =
respectively. I verified this value in lk 2.4.30 also, these values are =
the same.

Though in lk 2.6.x, the values have been hardcoded in the =
arch/ppc/platforms/ibm440gx.c to 0x0000000140000b50 and =
0x0000000140000d50. Therefore, the confusion.

I hope this clears your misunderstanding. I did not see your suggestion =
for using your version of 2.4.x backported driver of ibm_emac. I could =
use it, if you send it again.

Thanks,
Sanjay

-----Original Message-----
From: Eugene Surovegin [mailto:ebs@ebshome.net]
Sent: Monday, May 23, 2005 4:04 PM
To: Sanjay Bajaj
Cc: linuxppc-embedded@ozlabs.org
Subject: Re: tah reset?


On Mon, May 23, 2005 at 03:17:26PM -0400, Sanjay Bajaj wrote:
> I did find the source of the reset tah issue. The physical address=20
> of TAH 0 and TAH 1 was ending in B00h and D00h respectively. But in=20
> the UM, it ends in B50 and D50. the file affected is ibm440gx.c in=20
> arch/ppc/platforms.

Linux 2.6 has correct values for TAH base address, 2.4 doesn't have=20
any support for TAH at all.

Where did you get this incorrect code?

You see, you should have used supported sources (2.6) or the one I=20
recommended to you (my 2.4 backport) but you have ignored this =20
suggestion and wasted your time and time of people on this mail list.

Please, next time if you use some stuff which isn't in kernel.org's=20
tree, direct you questions to the person who made those patches,=20
because we cannot help you as we don't have the source code you are=20
using.

--=20
Eugene

RE: tah reset?

[Sanjay Bajaj]

Eugene,

Yes, TAH0 in SDR0_MFR register is enabled.

EMAC is able to reset correctly, but TAH isn't at the same location [in =
emac_probe()]. PHY is connected to EMAC and TAH is behind EMAC. I do not =
understand how the RX clock from PHY will reach TAH? Any suggestions ?

Thanks,
Sanjay

-----Original Message-----
From: Eugene Surovegin [mailto:ebs@ebshome.net]
Sent: Thursday, May 19, 2005 2:23 PM
To: Sanjay Bajaj
Cc: linuxppc-embedded@ozlabs.org
Subject: Re: tah reset?


On Thu, May 19, 2005 at 02:14:20PM -0400, Sanjay Bajaj wrote:
> While trying to reset the TAH on emac2 of PPC440GX, the Soft Reset=20
> (SR) bit never resets itself to 0. Does anybody know the reason for=20
> it?

Did you enable TAH0 in SDR0_MFR register?

Also, I don't remember for sure, but TAH may have the same problem as=20
EMAC, namely, it won't go out of reset if there is no RX clock from=20
PHY.

--=20
Eugene

Re: tah reset?

[Eugene Surovegin]

On Thu, May 19, 2005 at 03:45:50PM -0400, Sanjay Bajaj wrote:
> Eugene,
> 
> Yes, TAH0 in SDR0_MFR register is enabled.
> 
> EMAC is able to reset correctly, but TAH isn't at the same location 
> [in emac_probe()]. PHY is connected to EMAC and TAH is behind EMAC. 
> I do not understand how the RX clock from PHY will reach TAH? Any suggestions ?

E.g. TAH RX path is clocked from the same source as EMAC, I think 
it's quite obvious, but I digress.

What are you doing? Having problems with EMAC driver? What kernel 
version? What board?

You can try my new NAPI EMAC driver (http://kernel.ebshome.net/).

-- 
Eugene

tah reset?

[Sanjay Bajaj]

While trying to reset the TAH on emac2 of PPC440GX, the Soft Reset (SR) =
bit never resets itself to 0. Does anybody know the reason for it?

Sanjay

Re: tah reset?

[Eugene Surovegin]

On Thu, May 19, 2005 at 02:14:20PM -0400, Sanjay Bajaj wrote:
> While trying to reset the TAH on emac2 of PPC440GX, the Soft Reset 
> (SR) bit never resets itself to 0. Does anybody know the reason for 
> it?

Did you enable TAH0 in SDR0_MFR register?

Also, I don't remember for sure, but TAH may have the same problem as 
EMAC, namely, it won't go out of reset if there is no RX clock from 
PHY.

-- 
Eugene