Enabling 8xx debug mode

[Marcelo Tosatti <marcelo.tosatti@cyclades.com>]

Hi Dan,

I know now that the BDI automatically enables debug mode by asserting
the DSCK signal (available through the JTAG port). Is there any way 
to enable debugging mode purely via software?

44.3.1.2 Entering Debug Mode

By appropriately programming the development port during reset, debug
mode can be entered immediately out of reset, thus allowing the user to
debug a ROM-less system. If DSCK is asserted throughout SRESET assertion
and then past SRESET negation, the processor takes a breakpoint
exception and goes directly to debug mode instead of fetching the reset
vector. To avoid entering debug mode after reset, DSCK must be negated
no later than seven clock cycles after SRESET negates, allowing the
processor to jump to the reset vector and begin normal execution. If
debug mode is entered immediately after reset, as shown in Figure 44-7,
ICR[DPI] is set. The user can enable events that can initiate debug mode
and determine which events require regular interrupt handling.