SRAM support for the Pegasos II platform

SRAM support for the Pegasos II platform

[Nicolas DET]

[-- Attachment #1: Type: text/plain, Size: 307 bytes --]

  Amiga............: SimpleMail   http://simplemail.sourceforge.net/
  Unix.............: Metamail     ftp://ftp.bellcore.com/nsb/
  Windows/Macintosh: Eudora       http://www.qualcomm.com/

General info about MIME can be found at:

http://www.cis.ohio-state.edu/hypertext/faq/usenet/mail/mime-faq/top.html

[-- Attachment #2: Type: text/plain, Size: 412 bytes --]

Hello,

You can find enclosed or at the URL a patch for the 2.6.14-rc1.
http://arrakin.homedns.org/~nicolas/mv643xx_eth_chrp_pegasos_eth.c.2.6.14-rc1.diff

It allows (with drivers/net/mv643xx_eth.*) to take advantage of the SRAM of
the Marvell Discovery II for the network driver.

Reviews and comments welcome.

I hope it could be include in upcomming 2.6.14.

Regards,
-- 
Nicolas DET
MorphOS & Linux developer

[-- Attachment #3: mv643xx_eth_chrp_pegasos_eth.c.2.6.14-rc1.diff --]
[-- Type: application/octet-stream, Size: 4868 bytes --]

--- linux-2.6.14-rc1/arch/ppc/platforms/chrp_pegasos_eth.c	2005-09-14 08:14:44.275127904 +0200
+++ linux-2.6.14-rc1_nico/arch/ppc/platforms/chrp_pegasos_eth.c	2005-09-14 10:48:26.566874500 +0200
@@ -17,6 +17,21 @@
 #include <linux/mv643xx.h>
 #include <linux/pci.h>
 
+// Pegasos II location and size for the SRAM stuff
+// Only used for the ethernet driver ATM
+#define PEGASOS2_MARVELL_REGBASE 		(0xf1000000)
+#define PEGASOS2_MARVELL_REGSIZE 		(0x00004000)
+#define PEGASOS2_SRAM_BASE 					(0xf2000000)
+#define PEGASOS2_SRAM_SIZE					(0x00008000)
+
+#define PEGASOS2_SRAM_BASE_ETH0			(PEGASOS2_SRAM_BASE)
+#define PEGASOS2_SRAM_BASE_ETH1			(PEGASOS2_SRAM_BASE_ETH0 + (PEGASOS2_SRAM_SIZE / 2) )
+
+#define PEGASOS2_SRAM_RXRING_SIZE		(PEGASOS2_SRAM_SIZE/4)
+#define PEGASOS2_SRAM_TXRING_SIZE		(PEGASOS2_SRAM_SIZE/4)
+
+//#define BE_VERBOSE
+
 /* Pegasos 2 specific Marvell MV 64361 gigabit ethernet port setup */
 static struct resource mv643xx_eth_shared_resources[] = {
 	[0] = {
@@ -44,7 +59,15 @@
 	},
 };
 
-static struct mv643xx_eth_platform_data eth0_pd;
+static struct mv643xx_eth_platform_data eth0_pd = {
+	.tx_sram_addr = PEGASOS2_SRAM_BASE_ETH0,
+	.tx_sram_size = PEGASOS2_SRAM_TXRING_SIZE,
+	.tx_queue_size = PEGASOS2_SRAM_TXRING_SIZE/16,
+	
+	.rx_sram_addr = PEGASOS2_SRAM_BASE + PEGASOS2_SRAM_TXRING_SIZE,
+	.rx_sram_size = PEGASOS2_SRAM_RXRING_SIZE,
+	.rx_queue_size = PEGASOS2_SRAM_RXRING_SIZE/16,
+};
 
 static struct platform_device eth0_device = {
 	.name		= MV643XX_ETH_NAME,
@@ -65,7 +88,15 @@
 	},
 };
 
-static struct mv643xx_eth_platform_data eth1_pd;
+static struct mv643xx_eth_platform_data eth1_pd = {
+	.tx_sram_addr = PEGASOS2_SRAM_BASE_ETH1,
+	.tx_sram_size = PEGASOS2_SRAM_TXRING_SIZE,
+	.tx_queue_size = PEGASOS2_SRAM_TXRING_SIZE/16,
+	
+	.rx_sram_addr = PEGASOS2_SRAM_BASE_ETH1 + PEGASOS2_SRAM_TXRING_SIZE,
+	.rx_sram_size = PEGASOS2_SRAM_RXRING_SIZE,
+	.rx_queue_size = PEGASOS2_SRAM_RXRING_SIZE/16,
+};
 
 static struct platform_device eth1_device = {
 	.name		= MV643XX_ETH_NAME,
@@ -83,7 +114,68 @@
 	&eth1_device,
 };
 
+/***********/
+/***********/
+#define MV_READ(offset,val) 	{ val = readl(mv643xx_reg_base + offset); }
+#define MV_WRITE(offset,data) writel(data, mv643xx_reg_base + offset)
+
+static void __iomem *mv643xx_reg_base = NULL;
+
 
+static int Enable_SRAM(void)
+{
+  u32 ALong;
+	
+	// Let's io remap the mv register to touch the SRAM config
+	if (mv643xx_reg_base == NULL)
+		mv643xx_reg_base = ioremap(PEGASOS2_MARVELL_REGBASE, PEGASOS2_MARVELL_REGSIZE);
+	
+	if (mv643xx_reg_base == NULL)
+		return -ENOMEM;
+
+#ifdef BE_VERBOSE
+	printk("Pegasos II/Marvell MV64361: register remapped from %p to %p\n", (void *)PEGASOS2_MARVELL_REGBASE, (void *)mv643xx_reg_base);
+#endif
+
+  // First the SRAM config register
+  // We set it to 0 ATM -> No cache coherency, no parity check
+  MV_WRITE(MV64340_SRAM_CONFIG, 0);
+
+  // set the SRAM address on the CPU side
+  MV_WRITE(MV64340_INTEGRATED_SRAM_BASE_ADDR, PEGASOS2_SRAM_BASE >> 16);
+
+  // Now enable it (CPU side)
+  MV_READ(MV64340_BASE_ADDR_ENABLE, ALong);
+  ALong &= ~(1 << 19);
+  MV_WRITE(MV64340_BASE_ADDR_ENABLE, ALong);
+
+  // And now to the GB side on WB 4 (0->3) can be use for DRAM stuff
+  ALong = 0x02; // Integrated SRAM value
+  ALong |= PEGASOS2_SRAM_BASE & 0xffff0000; // Finally set the SRAM adress in the uppter par of the register
+  MV_WRITE(MV643XX_ETH_BAR_4, ALong);
+
+  // and the size ...
+  MV_WRITE(MV643XX_ETH_SIZE_REG_4, PEGASOS2_SRAM_SIZE & 0xffff0000);
+
+  // Finaly enable the window
+  MV_READ(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong);
+  ALong &= ~(1 << 4);
+  MV_WRITE(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong);
+
+#ifdef BE_VERBOSE
+	printk("Pegasos II/Marvell MV64361: register unmapped\n");
+	printk("Pegasos II/Marvell MV64361: SRAM at %p, size=%x\n", (void*) PEGASOS2_SRAM_BASE, PEGASOS2_SRAM_SIZE);
+#endif
+
+	iounmap(mv643xx_reg_base);
+	mv643xx_reg_base = NULL;
+
+  return 1;
+}
+
+
+/***********/
+/***********/
 int
 mv643xx_eth_add_pds(void)
 {
@@ -93,9 +185,38 @@
 		{ }
 	};
 
-	if (pci_dev_present(pci_marvell_mv64360)) {
+#ifdef BE_VERBOSE
+	printk("Pegasos II/Marvell MV64361: init\n");
+#endif
+
+	if (pci_dev_present(pci_marvell_mv64360))
+	{
 		ret = platform_add_devices(mv643xx_eth_pd_devs, ARRAY_SIZE(mv643xx_eth_pd_devs));
+		
+		if ( Enable_SRAM() < 0)
+		{
+			// Humm, disable SRAM stuff
+			eth0_pd.tx_sram_addr = 0;
+			eth0_pd.tx_sram_size = 0;
+			eth0_pd.rx_sram_addr = 0;
+			eth0_pd.rx_sram_size = 0;
+			
+			eth1_pd.tx_sram_addr = 0;
+			eth1_pd.tx_sram_size = 0;
+			eth1_pd.rx_sram_addr = 0;
+			eth1_pd.rx_sram_size = 0;
+			
+#ifdef BE_VERBOSE
+			printk("Pegasos II/Marvell MV64361: Can't enable the SRAM\n");
+#endif
+		}	
 	}
+	
+#ifdef BE_VERBOSE
+		
+	printk("Pegasos II/Marvell MV64361: init is over\n");
+#endif
+	
 	return ret;
 }
 device_initcall(mv643xx_eth_add_pds);

Re: SRAM support for the Pegasos II platform

[Dale Farnsworth]

In article <20050914091229.A27721C007F7@mwinf0309.wanadoo.fr> you write:
> You can find enclosed or at the URL a patch for the 2.6.14-rc1.
> http://arrakin.homedns.org/~nicolas/mv643xx_eth_chrp_pegasos_eth.c.2.6.14-rc1.diff
> 
> It allows (with drivers/net/mv643xx_eth.*) to take advantage of the SRAM of
> the Marvell Discovery II for the network driver.
> 
> Reviews and comments welcome.

Hi Nicolas,

+#define PEGASOS2_SRAM_SIZE				(0x00008000)

I think the SRAM is 256KB, so shouldn't this be 0x00040000 ?

-Dale

Re: SRAM support for the Pegasos II platform

[Andrew Morton]

Nicolas DET <det.nicolas@free.fr> wrote:
>
> You can find enclosed or at the URL a patch for the 2.6.14-rc1.
> http://arrakin.homedns.org/~nicolas/mv643xx_eth_chrp_pegasos_eth.c.2.6.14-rc1.diff
> 
> It allows (with drivers/net/mv643xx_eth.*) to take advantage of the SRAM of
> the Marvell Discovery II for the network driver.

I've kind of lost the plot with what happened with this patch.  Who is the
maintainer of this driver, and has [s]he commented on this patch?

The patch does strange things with whitespace: some places it uses spaces,
other places it uses tabs.  Please fix that up using hard tabs and resend. 
When doing so, please first review
http://www.zip.com.au/~akpm/linux/patches/stuff/tpp.txt for the patch
preparation protocol, thanks.

Re: SRAM support for the Pegasos II platform

[Dale Farnsworth]

On Tue, Oct 11, 2005 at 08:50:22PM +0000, Andrew Morton wrote:
> Nicolas DET <det.nicolas@free.fr> wrote:
> >
> > You can find enclosed or at the URL a patch for the 2.6.14-rc1.
> > http://arrakin.homedns.org/~nicolas/mv643xx_eth_chrp_pegasos_eth.c.2.6.14-rc1.diff
> > 
> > It allows (with drivers/net/mv643xx_eth.*) to take advantage of the SRAM of
> > the Marvell Discovery II for the network driver.
> 
> I've kind of lost the plot with what happened with this patch.  Who is the
> maintainer of this driver, and has [s]he commented on this patch?

I'm the maintainer of the 2.6 mv643xx_eth driver.  The only comment I had
(in http://ozlabs.org/pipermail/linuxppc-dev/2005-September/019764.html)
was that the define for PEGASOS2_SRAM_SIZE looks wrong.  When that and
the whitespace/style issues are fixed, I'm OK with the change.

-Dale