* [PATCH 0/4] 440SPe support
@ 2005-09-23 3:03 Roland Dreier
2005-09-23 3:03 ` [PATCH 1/4] [PPC32] Allow ERPN for early serial to depend on CPU type Roland Dreier
0 siblings, 1 reply; 23+ messages in thread
From: Roland Dreier @ 2005-09-23 3:03 UTC (permalink / raw)
To: mporter; +Cc: linuxppc-embedded
Here is a series of patches that add basic support for AMCC's PowerPC
440SPe SoC. With these patches, the kernel will boot and run on the
"Yucca" 440SPe eval board, with ethernet and serial working.
I don't have PCI-X or PCI Express in a mergeable state, but I thought
it would be worth posting these now for review. Also, it would
probably be good to figure out how we want to merge this upstream once
2.6.14 comes out -- 440SPe requires some minor changes to ethernet PHY
handling, which will have to be coordinated with the ibm_emac rewrite,
and there are also some minor conflicts with the 440GR patches I saw.
Right now I'm working on PCI Express support, and I'll post those
patches once I have something reasonable.
I also have a git tree at
rsync://rsync.kernel.org/pub/scm/linux/kernel/git/roland/ppc440spe.git
that contains all of these patches, in case that makes it easier to
merge this stuff.
Thanks,
Roland
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 1/4] [PPC32] Allow ERPN for early serial to depend on CPU type 2005-09-23 3:03 [PATCH 0/4] 440SPe support Roland Dreier @ 2005-09-23 3:03 ` Roland Dreier 2005-09-23 3:03 ` [PATCH 2/4] [PPC32] Add 440SPe support Roland Dreier 0 siblings, 1 reply; 23+ messages in thread From: Roland Dreier @ 2005-09-23 3:03 UTC (permalink / raw) To: mporter; +Cc: linuxppc-embedded The PowerPC 440SPe supports up to 16 GB of RAM, and therefore its IO registers are at 0x4_xxxx_xxxx instead of being at 0x1_xxxx_xxxx like most other PPC 440 chips. To allow for this, this patch moves the definition of the ERPN used for mapping UART0 from being hard-coded in the head_44x.S assembly code to being defined in ibm44x.h. Signed-off-by: Roland Dreier <rolandd@cisco.com> --- arch/ppc/kernel/head_44x.S | 4 ++-- include/asm-ppc/ibm44x.h | 7 ++++++- 2 files changed, 8 insertions(+), 3 deletions(-) eb79641bc2a92b7d4c2f62e072650e20a7748f45 diff --git a/arch/ppc/kernel/head_44x.S b/arch/ppc/kernel/head_44x.S --- a/arch/ppc/kernel/head_44x.S +++ b/arch/ppc/kernel/head_44x.S @@ -190,8 +190,8 @@ skpinv: addi r4,r4,1 /* Increment */ /* xlat fields */ lis r4,UART0_PHYS_IO_BASE@h /* RPN depends on SoC */ -#ifndef CONFIG_440EP - ori r4,r4,0x0001 /* ERPN is 1 for second 4GB page */ +#ifdef UART0_PHYS_ERPN + ori r4,r4,UART0_PHYS_ERPN /* Add ERPN if above 4GB */ #endif /* attrib fields */ diff --git a/include/asm-ppc/ibm44x.h b/include/asm-ppc/ibm44x.h --- a/include/asm-ppc/ibm44x.h +++ b/include/asm-ppc/ibm44x.h @@ -34,12 +34,17 @@ /* Lowest TLB slot consumed by the default pinned TLBs */ #define PPC44x_LOW_SLOT 63 -/* LS 32-bits of UART0 physical address location for early serial text debug */ +/* + * Least significant 32-bits and extended real page number (ERPN) of + * UART0 physical address location for early serial text debug + */ #if defined(CONFIG_440SP) +#define UART0_PHYS_ERPN 1 #define UART0_PHYS_IO_BASE 0xf0000200 #elif defined(CONFIG_440EP) #define UART0_PHYS_IO_BASE 0xe0000000 #else +#define UART0_PHYS_ERPN 1 #define UART0_PHYS_IO_BASE 0x40000200 #endif ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 2/4] [PPC32] Add 440SPe support 2005-09-23 3:03 ` [PATCH 1/4] [PPC32] Allow ERPN for early serial to depend on CPU type Roland Dreier @ 2005-09-23 3:03 ` Roland Dreier 2005-09-23 3:03 ` [PATCH 3/4] [PPC32] ibm_emac: " Roland Dreier ` (2 more replies) 0 siblings, 3 replies; 23+ messages in thread From: Roland Dreier @ 2005-09-23 3:03 UTC (permalink / raw) To: mporter; +Cc: linuxppc-embedded Add support for the AMCC PowerPC 440SPe SoC. Signed-off-by: Roland Dreier <rolandd@cisco.com> --- arch/ppc/kernel/cputable.c | 10 +++ arch/ppc/platforms/4xx/Kconfig | 8 ++ arch/ppc/platforms/4xx/Makefile | 1 arch/ppc/platforms/4xx/amcc440spe.c | 134 +++++++++++++++++++++++++++++++++++ arch/ppc/platforms/4xx/amcc440spe.h | 64 +++++++++++++++++ arch/ppc/syslib/Makefile | 1 arch/ppc/syslib/ibm440sp_common.c | 4 + arch/ppc/syslib/ppc4xx_pic.c | 38 ++++++++++ include/asm-ppc/ibm44x.h | 42 ++++++++--- 9 files changed, 287 insertions(+), 15 deletions(-) create mode 100644 arch/ppc/platforms/4xx/amcc440spe.c create mode 100644 arch/ppc/platforms/4xx/amcc440spe.h 4d773d76476fd1f577d1c7755c24d973fbfc1fe5 diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c --- a/arch/ppc/kernel/cputable.c +++ b/arch/ppc/kernel/cputable.c @@ -972,6 +972,16 @@ struct cpu_spec cpu_specs[] = { .icache_bsize = 32, .dcache_bsize = 32, }, + { /* 440SPe Rev. A */ + .pvr_mask = 0xff000fff, + .pvr_value = 0x53000890, + .cpu_name = "440SPe Rev. A", + .cpu_features = CPU_FTR_SPLIT_ID_CACHE | + CPU_FTR_USE_TB, + .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, + .icache_bsize = 32, + .dcache_bsize = 32, + }, #endif /* CONFIG_44x */ #ifdef CONFIG_FSL_BOOKE { /* e200z5 */ diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig --- a/arch/ppc/platforms/4xx/Kconfig +++ b/arch/ppc/platforms/4xx/Kconfig @@ -124,9 +124,13 @@ config 440SP depends on LUAN default y +config 440SPE + bool + default n + config 440 bool - depends on 440GP || 440SP || 440EP + depends on 440GP || 440SP || 440SPE || 440EP default y config 440A @@ -168,7 +172,7 @@ config XILINX_OCP config IBM_EMAC4 bool - depends on 440GX || 440SP + depends on 440GX || 440SP || 440SPE default y config BIOS_FIXUP diff --git a/arch/ppc/platforms/4xx/Makefile b/arch/ppc/platforms/4xx/Makefile --- a/arch/ppc/platforms/4xx/Makefile +++ b/arch/ppc/platforms/4xx/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_440EP) += ibm440ep.o obj-$(CONFIG_440GP) += ibm440gp.o obj-$(CONFIG_440GX) += ibm440gx.o obj-$(CONFIG_440SP) += ibm440sp.o +obj-$(CONFIG_440SPE) += amcc440spe.o obj-$(CONFIG_405EP) += ibm405ep.o obj-$(CONFIG_405GPR) += ibm405gpr.o obj-$(CONFIG_VIRTEX_II_PRO) += virtex-ii_pro.o diff --git a/arch/ppc/platforms/4xx/amcc440spe.c b/arch/ppc/platforms/4xx/amcc440spe.c new file mode 100644 --- /dev/null +++ b/arch/ppc/platforms/4xx/amcc440spe.c @@ -0,0 +1,134 @@ +/* + * arch/ppc/platforms/4xx/amc440spe.c + * + * PPC440SPe I/O descriptions + * + * Roland Dreier <rolandd@cisco.com> + * Copyright (c) 2005 Cisco Systems. All rights reserved. + * + * Matt Porter <mporter@kernel.crashing.org> + * Copyright 2002-2005 MontaVista Software Inc. + * + * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net> + * Copyright (c) 2003, 2004 Zultys Technologies + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ +#include <linux/init.h> +#include <linux/module.h> +#include <platforms/4xx/amcc440spe.h> +#include <asm/ocp.h> + +static struct ocp_func_emac_data amc440spe_emac0_def = { + .rgmii_idx = -1, /* No RGMII */ + .rgmii_mux = -1, /* No RGMII */ + .zmii_idx = -1, /* No ZMII */ + .zmii_mux = -1, /* No ZMII */ + .mal_idx = 0, /* MAL device index */ + .mal_rx_chan = 0, /* MAL rx channel number */ + .mal_tx_chan = 0, /* MAL tx channel number */ + .wol_irq = 61, /* WOL interrupt number */ + .mdio_idx = -1, /* No shared MDIO */ + .tah_idx = -1, /* No TAH */ + .jumbo = 1, /* Jumbo frames supported */ +}; +OCP_SYSFS_EMAC_DATA() + +static struct ocp_func_mal_data amc440spe_mal0_def = { + .num_tx_chans = 1, /* Number of TX channels */ + .num_rx_chans = 1, /* Number of RX channels */ + .txeob_irq = 38, /* TX End Of Buffer IRQ */ + .rxeob_irq = 39, /* RX End Of Buffer IRQ */ + .txde_irq = 34, /* TX Descriptor Error IRQ */ + .rxde_irq = 35, /* RX Descriptor Error IRQ */ + .serr_irq = 33, /* MAL System Error IRQ */ +}; +OCP_SYSFS_MAL_DATA() + +static struct ocp_func_iic_data amc440spe_iic0_def = { + .fast_mode = 0, /* Use standad mode (100Khz) */ +}; + +static struct ocp_func_iic_data amc440spe_iic1_def = { + .fast_mode = 0, /* Use standad mode (100Khz) */ +}; +OCP_SYSFS_IIC_DATA() + +struct ocp_def core_ocp[] = { + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_OPB, + .index = 0, + .paddr = 0x0000000140000000ULL, + .irq = OCP_IRQ_NA, + .pm = OCP_CPM_NA, + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_16550, + .index = 0, + .paddr = PPC440SPE_UART0_ADDR, + .irq = UART0_INT, + .pm = IBM_CPM_UART0, + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_16550, + .index = 1, + .paddr = PPC440SPE_UART1_ADDR, + .irq = UART1_INT, + .pm = IBM_CPM_UART1, + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_16550, + .index = 2, + .paddr = PPC440SPE_UART2_ADDR, + .irq = UART2_INT, + .pm = IBM_CPM_UART2, + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_IIC, + .index = 0, + .paddr = 0x00000001f0000400ULL, + .irq = 2, + .pm = IBM_CPM_IIC0, + .additions = &amc440spe_iic0_def, + .show = &ocp_show_iic_data + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_IIC, + .index = 1, + .paddr = 0x00000001f0000500ULL, + .irq = 3, + .pm = IBM_CPM_IIC1, + .additions = &amc440spe_iic1_def, + .show = &ocp_show_iic_data + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_GPIO, + .index = 0, + .paddr = 0x00000001f0000700ULL, + .irq = OCP_IRQ_NA, + .pm = IBM_CPM_GPIO0, + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_MAL, + .paddr = OCP_PADDR_NA, + .irq = OCP_IRQ_NA, + .pm = OCP_CPM_NA, + .additions = &amc440spe_mal0_def, + .show = &ocp_show_mal_data, + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_EMAC, + .index = 0, + .paddr = 0x00000004f0000800ULL, + .irq = 60, + .pm = OCP_CPM_NA, + .additions = &amc440spe_emac0_def, + .show = &ocp_show_emac_data, + }, + { .vendor = OCP_VENDOR_INVALID + } +}; diff --git a/arch/ppc/platforms/4xx/amcc440spe.h b/arch/ppc/platforms/4xx/amcc440spe.h new file mode 100644 --- /dev/null +++ b/arch/ppc/platforms/4xx/amcc440spe.h @@ -0,0 +1,64 @@ +/* + * arch/ppc/platforms/4xx/ibm440sp.h + * + * PPC440SP definitions + * + * Matt Porter <mporter@kernel.crashing.org> + * + * Copyright 2004-2005 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifdef __KERNEL__ +#ifndef __PPC_PLATFORMS_AMCC440SPE_H +#define __PPC_PLATFORMS_AMCC440SPE_H + +#include <linux/config.h> + +#include <asm/ibm44x.h> + +/* UART */ +#define PPC440SPE_UART0_ADDR 0x00000004f0000200ULL +#define PPC440SPE_UART1_ADDR 0x00000004f0000300ULL +#define PPC440SPE_UART2_ADDR 0x00000004f0000600ULL +#define UART0_INT 0 +#define UART1_INT 1 +#define UART2_INT 37 + +/* Clock and Power Management */ +#define IBM_CPM_IIC0 0x80000000 /* IIC interface */ +#define IBM_CPM_IIC1 0x40000000 /* IIC interface */ +#define IBM_CPM_PCI 0x20000000 /* PCI bridge */ +#define IBM_CPM_CPU 0x02000000 /* processor core */ +#define IBM_CPM_DMA 0x01000000 /* DMA controller */ +#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */ +#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */ +#define IBM_CPM_EBC 0x00200000 /* External Bux Controller */ +#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */ +#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */ +#define IBM_CPM_PLB 0x00040000 /* PLB bus arbiter */ +#define IBM_CPM_SRAM 0x00020000 /* SRAM memory controller */ +#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */ +#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */ +#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */ +#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */ +#define IBM_CPM_UART0 0x00000200 /* serial port 0 */ +#define IBM_CPM_UART1 0x00000100 /* serial port 1 */ +#define IBM_CPM_UART2 0x00000100 /* serial port 1 */ +#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */ +#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */ +#define IBM_CPM_EMAC0 0x00000020 /* EMAC 0 */ + +#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \ + | IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \ + | IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \ + | IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI \ + | IBM_CPM_TAHOE0 | IBM_CPM_TAHOE1 \ + | IBM_CPM_EMAC0 | IBM_CPM_EMAC1 \ + | IBM_CPM_EMAC2 | IBM_CPM_EMAC3 ) +#endif /* __PPC_PLATFORMS_AMCC440SP_H */ +#endif /* __KERNEL__ */ diff --git a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile --- a/arch/ppc/syslib/Makefile +++ b/arch/ppc/syslib/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_440EP) += ibm440gx_common. obj-$(CONFIG_440GP) += ibm440gp_common.o obj-$(CONFIG_440GX) += ibm440gx_common.o obj-$(CONFIG_440SP) += ibm440gx_common.o ibm440sp_common.o +obj-$(CONFIG_440SPE) += ibm440gx_common.o ibm440sp_common.o ifeq ($(CONFIG_4xx),y) ifeq ($(CONFIG_VIRTEX_II_PRO),y) obj-$(CONFIG_40x) += xilinx_pic.o diff --git a/arch/ppc/syslib/ibm440sp_common.c b/arch/ppc/syslib/ibm440sp_common.c --- a/arch/ppc/syslib/ibm440sp_common.c +++ b/arch/ppc/syslib/ibm440sp_common.c @@ -1,7 +1,7 @@ /* * arch/ppc/syslib/ibm440sp_common.c * - * PPC440SP system library + * PPC440SP/PPC440SPe system library * * Matt Porter <mporter@kernel.crashing.org> * Copyright 2002-2005 MontaVista Software Inc. @@ -35,7 +35,7 @@ unsigned long __init ibm440sp_find_end_o u32 mem_size = 0; /* Read two bank sizes and sum */ - for (i=0; i<2; i++) + for (i=0; i< MQ0_NUM_BANKS; i++) switch (mfdcr(DCRN_MQ0_BS0BAS + i) & MQ0_CONFIG_SIZE_MASK) { case MQ0_CONFIG_SIZE_8M: mem_size += PPC44x_MEM_SIZE_8M; diff --git a/arch/ppc/syslib/ppc4xx_pic.c b/arch/ppc/syslib/ppc4xx_pic.c --- a/arch/ppc/syslib/ppc4xx_pic.c +++ b/arch/ppc/syslib/ppc4xx_pic.c @@ -37,6 +37,7 @@ extern unsigned char ppc4xx_uic_ext_irq_ #define IRQ_MASK_UICx(irq) (1 << (31 - ((irq) & 0x1f))) #define IRQ_MASK_UIC1(irq) IRQ_MASK_UICx(irq) #define IRQ_MASK_UIC2(irq) IRQ_MASK_UICx(irq) +#define IRQ_MASK_UIC3(irq) IRQ_MASK_UICx(irq) #define UIC_HANDLERS(n) \ static void ppc4xx_uic##n##_enable(unsigned int irq) \ @@ -87,7 +88,39 @@ static void ppc4xx_uic##n##_end(unsigned .end = ppc4xx_uic##n##_end, \ } \ -#if NR_UICS == 3 +#if NR_UICS == 4 +#define ACK_UIC0_PARENT +#define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC); +#define ACK_UIC2_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC2NC); +#define ACK_UIC3_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC3NC); +UIC_HANDLERS(0); +UIC_HANDLERS(1); +UIC_HANDLERS(2); +UIC_HANDLERS(3); + +static int ppc4xx_pic_get_irq(struct pt_regs *regs) +{ + u32 uic0 = mfdcr(DCRN_UIC_MSR(UIC0)); + if (uic0 & UIC0_UIC1NC) + return 64 - ffs(mfdcr(DCRN_UIC_MSR(UIC1))); + else if (uic0 & UIC0_UIC2NC) + return 96 - ffs(mfdcr(DCRN_UIC_MSR(UIC2))); + else if (uic0 & UIC0_UIC2NC) + return 128 - ffs(mfdcr(DCRN_UIC_MSR(UIC3))); + else + return uic0 ? 32 - ffs(uic0) : -1; +} + +static void __init ppc4xx_pic_impl_init(void) +{ + /* Enable cascade interrupts in UIC0 */ + /* Enable cascade interrupt in UIC0 */ + ppc_cached_irq_mask[0] |= UIC0_UIC1NC | UIC0_UIC2NC | UIC0_UIC3NC; + mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC | UIC0_UIC2NC | UIC0_UIC3NC); + mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[0]); +} + +#elif NR_UICS == 3 #define ACK_UIC0_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC0NC); #define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC1NC); #define ACK_UIC2_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC2NC); @@ -169,6 +202,9 @@ static struct ppc4xx_uic_impl { { .decl = DECLARE_UIC(1), .base = UIC1 }, #if NR_UICS > 2 { .decl = DECLARE_UIC(2), .base = UIC2 }, +#if NR_UICS > 3 + { .decl = DECLARE_UIC(3), .base = UIC3 }, +#endif #endif #endif }; diff --git a/include/asm-ppc/ibm44x.h b/include/asm-ppc/ibm44x.h --- a/include/asm-ppc/ibm44x.h +++ b/include/asm-ppc/ibm44x.h @@ -41,6 +41,9 @@ #if defined(CONFIG_440SP) #define UART0_PHYS_ERPN 1 #define UART0_PHYS_IO_BASE 0xf0000200 +#elif defined(CONFIG_440SPE) +#define UART0_PHYS_ERPN 4 +#define UART0_PHYS_IO_BASE 0xf0000200 #elif defined(CONFIG_440EP) #define UART0_PHYS_IO_BASE 0xe0000000 #else @@ -76,7 +79,7 @@ /* * 36-bit trap ranges */ -#if defined(CONFIG_440SP) +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) #define PPC44x_IO_LO 0xf0000000UL #define PPC44x_IO_HI 0xf0000fffUL #define PPC44x_PCI0CFG_LO 0x0ec00000UL @@ -114,7 +117,7 @@ */ -/* CPRs (440GX and 440SP) */ +/* CPRs (440GX and 440SP/440SPe) */ #define DCRN_CPR_CONFIG_ADDR 0xc #define DCRN_CPR_CONFIG_DATA 0xd @@ -135,7 +138,7 @@ mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \ mtdcr(DCRN_CPR_CONFIG_DATA, data);}) -/* SDRs (440GX and 440SP) */ +/* SDRs (440GX and 440SP/440SPe) */ #define DCRN_SDR_CONFIG_ADDR 0xe #define DCRN_SDR_CONFIG_DATA 0xf #define DCRN_SDR_PFC0 0x4100 @@ -185,7 +188,7 @@ mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \ mtdcr(DCRN_SDR_CONFIG_DATA,data);}) -/* DMA (excluding 440SP) */ +/* DMA (excluding 440SP/440SPe) */ #define DCRN_DMA0_BASE 0x100 #define DCRN_DMA1_BASE 0x108 #define DCRN_DMA2_BASE 0x110 @@ -205,12 +208,20 @@ /* UIC */ #define DCRN_UIC0_BASE 0xc0 #define DCRN_UIC1_BASE 0xd0 -#define DCRN_UIC2_BASE 0x210 -#define DCRN_UICB_BASE 0x200 #define UIC0 DCRN_UIC0_BASE #define UIC1 DCRN_UIC1_BASE + +#ifdef CONFIG_440SPE +#define DCRN_UIC2_BASE 0xe0 +#define DCRN_UIC3_BASE 0xf0 +#define UIC2 DCRN_UIC2_BASE +#define UIC3 DCRN_UIC3_BASE +#else +#define DCRN_UIC2_BASE 0x210 +#define DCRN_UICB_BASE 0x200 #define UIC2 DCRN_UIC2_BASE #define UICB DCRN_UICB_BASE +#endif #define DCRN_UIC_SR(base) (base + 0x0) #define DCRN_UIC_ER(base) (base + 0x2) @@ -223,6 +234,12 @@ #define UIC0_UIC1NC 0x00000002 +#ifdef CONFIG_440SPE +#define UIC0_UIC1NC 0x00000002 +#define UIC0_UIC2NC 0x00008000 +#define UIC0_UIC3NC 0x00200000 +#endif + #define UICB_UIC0NC 0x40000000 #define UICB_UIC1NC 0x10000000 #define UICB_UIC2NC 0x04000000 @@ -412,9 +429,13 @@ #define PPC44x_MEM_SIZE_1G 0x40000000 #define PPC44x_MEM_SIZE_2G 0x80000000 -/* 440SP memory controller DCRs */ +/* 440SP/440SPe memory controller DCRs */ #define DCRN_MQ0_BS0BAS 0x40 -#define DCRN_MQ0_BS1BAS 0x41 +#if defined(CONFIG_440SP) +#define MQ0_NUM_BANKS 2 +#elif defined(CONFIG_440SPE) +#define MQ0_NUM_BANKS 4 +#endif #define MQ0_CONFIG_SIZE_MASK 0x0000fff0 #define MQ0_CONFIG_SIZE_8M 0x0000ffc0 @@ -426,8 +447,9 @@ #define MQ0_CONFIG_SIZE_512M 0x0000f000 #define MQ0_CONFIG_SIZE_1G 0x0000e000 #define MQ0_CONFIG_SIZE_2G 0x0000c000 +#define MQ0_CONFIG_SIZE_4G 0x00008000 -/* Internal SRAM Controller 440GX/440SP */ +/* Internal SRAM Controller 440GX/440SP/440SPe */ #define DCRN_SRAM0_BASE 0x000 #define DCRN_SRAM0_SB0CR (DCRN_SRAM0_BASE + 0x020) @@ -451,7 +473,7 @@ #define DCRN_SRAM0_DPC (DCRN_SRAM0_BASE + 0x02a) #define SRAM_DPC_ENABLE 0x80000000 -/* L2 Cache Controller 440GX/440SP */ +/* L2 Cache Controller 440GX/440SP/440SPe */ #define DCRN_L2C0_CFG 0x030 #define L2C_CFG_L2M 0x80000000 #define L2C_CFG_ICU 0x40000000 ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 3/4] [PPC32] ibm_emac: Add 440SPe support 2005-09-23 3:03 ` [PATCH 2/4] [PPC32] Add 440SPe support Roland Dreier @ 2005-09-23 3:03 ` Roland Dreier 2005-09-23 3:03 ` [PATCH 4/4] [PPC32] Add Yucca (440SPe eval board) platform Roland Dreier 2005-09-23 3:22 ` [PATCH 3/4] [PPC32] ibm_emac: Add 440SPe support Eugene Surovegin 2005-09-23 3:29 ` [PATCH 2/4] [PPC32] " Eugene Surovegin 2005-09-23 17:20 ` Matt Porter 2 siblings, 2 replies; 23+ messages in thread From: Roland Dreier @ 2005-09-23 3:03 UTC (permalink / raw) To: mporter; +Cc: linuxppc-embedded Eugene, I'm not sure what the status of your ibm_emac rewrite is. Is there a tree somewhere that you would like me to merge this change with and then send you a patch, or do you want to take care of merging? For some reason, the hardware designers made the polarity of one bit in the 440SPe's PHY interface register the opposite of all other PPC 440 chips. To handle this, abstract our access to this bit into emac_phy_start() and emac_phy_done() functions, and do the right thing based on the configured CPU type. Signed-off-by: Roland Dreier <rolandd@cisco.com> --- drivers/net/ibm_emac/ibm_emac.h | 2 - drivers/net/ibm_emac/ibm_emac_core.c | 72 ++++++++++++++++++++++++++-------- 2 files changed, 55 insertions(+), 19 deletions(-) 187bfbe2d410e5a229fb828e2c3dd0a8045857e8 diff --git a/drivers/net/ibm_emac/ibm_emac.h b/drivers/net/ibm_emac/ibm_emac.h --- a/drivers/net/ibm_emac/ibm_emac.h +++ b/drivers/net/ibm_emac/ibm_emac.h @@ -237,7 +237,7 @@ typedef struct emac_regs { #define EMAC_RWMR_DEFAULT 0x1000a200 #define EMAC_TMR0_DEFAULT EMAC_TMR0_TFAE_2_32 #define EMAC_TMR1_DEFAULT 0xa00f0000 -#elif defined(CONFIG_440SP) +#elif defined(CONFIG_440SP) || defined(CONFIG_440SPE) #define EMAC_RWMR_DEFAULT 0x08002000 #define EMAC_TMR0_DEFAULT EMAC_TMR0_TFAE_128_2048 #define EMAC_TMR1_DEFAULT 0xf8200000 diff --git a/drivers/net/ibm_emac/ibm_emac_core.c b/drivers/net/ibm_emac/ibm_emac_core.c --- a/drivers/net/ibm_emac/ibm_emac_core.c +++ b/drivers/net/ibm_emac/ibm_emac_core.c @@ -160,6 +160,34 @@ static struct net_device_stats *emac_sta return &fep->stats; }; +/* + * For the 440SPe, AMCC inexplicably changed the polarity of + * the "operation complete" bit in the MII control register. + */ +#ifdef CONFIG_440SPE +static inline int emac_phy_done(uint32_t stacr) +{ + return !(stacr & EMAC_STACR_OC); +}; + +static inline uint32_t emac_phy_start(uint32_t stacr) +{ + return stacr | EMAC_STACR_OC; +}; + +#else /* CONFIG_440SPE */ + +static inline int emac_phy_done(uint32_t stacr) +{ + return stacr & EMAC_STACR_OC; +}; + +static inline uint32_t emac_phy_start(uint32_t stacr) +{ + return stacr; +}; +#endif /* CONFIG_440SPE */ + static int emac_init_rgmii(struct ocp_device *rgmii_dev, int input, int phy_mode) { @@ -397,13 +425,15 @@ int emac_phy_read(struct net_device *dev emacp = fep->emacp; } - count = 0; - while ((((stacr = in_be32(&emacp->em0stacr)) & EMAC_STACR_OC) == 0) - && (count++ < MDIO_DELAY)) + for (count = 0; count < MDIO_DELAY; ++count) { + stacr = in_be32(&emacp->em0stacr); + if (emac_phy_done(stacr)) + break; udelay(1); + } MDIO_DEBUG((" (count was %d)\n", count)); - if ((stacr & EMAC_STACR_OC) == 0) { + if (!emac_phy_done(stacr)) { printk(KERN_WARNING "%s: PHY read timeout #1!\n", dev->name); return -1; } @@ -412,15 +442,17 @@ int emac_phy_read(struct net_device *dev stacr = ((EMAC_STACR_READ | (reg & 0x1f)) & ~EMAC_STACR_CLK_100MHZ); stacr |= ((mii_id & 0x1F) << 5); - out_be32(&emacp->em0stacr, stacr); + out_be32(&emacp->em0stacr, emac_phy_start(stacr)); - count = 0; - while ((((stacr = in_be32(&emacp->em0stacr)) & EMAC_STACR_OC) == 0) - && (count++ < MDIO_DELAY)) + for (count = 0; count < MDIO_DELAY; ++count) { + stacr = in_be32(&emacp->em0stacr); + if (emac_phy_done(stacr)) + break; udelay(1); + } MDIO_DEBUG((" (count was %d)\n", count)); - if ((stacr & EMAC_STACR_OC) == 0) { + if (!emac_phy_done(stacr)) { printk(KERN_WARNING "%s: PHY read timeout #2!\n", dev->name); return -1; } @@ -457,13 +489,15 @@ void emac_phy_write(struct net_device *d emacp = fep->emacp; } - count = 0; - while ((((stacr = in_be32(&emacp->em0stacr)) & EMAC_STACR_OC) == 0) - && (count++ < MDIO_DELAY)) + for (count = 0; count < MDIO_DELAY; ++count) { + stacr = in_be32(&emacp->em0stacr); + if (emac_phy_done(stacr)) + break; udelay(1); + } MDIO_DEBUG((" (count was %d)\n", count)); - if ((stacr & EMAC_STACR_OC) == 0) { + if (!emac_phy_done(stacr)) { printk(KERN_WARNING "%s: PHY write timeout #2!\n", dev->name); return; } @@ -473,15 +507,17 @@ void emac_phy_write(struct net_device *d stacr = ((EMAC_STACR_WRITE | (reg & 0x1f)) & ~EMAC_STACR_CLK_100MHZ); stacr |= ((mii_id & 0x1f) << 5) | ((data & 0xffff) << 16); - out_be32(&emacp->em0stacr, stacr); + out_be32(&emacp->em0stacr, emac_phy_start(stacr)); - count = 0; - while ((((stacr = in_be32(&emacp->em0stacr)) & EMAC_STACR_OC) == 0) - && (count++ < MDIO_DELAY)) + for (count = 0; count < MDIO_DELAY; ++count) { + stacr = in_be32(&emacp->em0stacr); + if (emac_phy_done(stacr)) + break; udelay(1); + } MDIO_DEBUG((" (count was %d)\n", count)); - if ((stacr & EMAC_STACR_OC) == 0) + if (!emac_phy_done(stacr)) printk(KERN_WARNING "%s: PHY write timeout #2!\n", dev->name); /* Check for a write error */ ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 4/4] [PPC32] Add Yucca (440SPe eval board) platform 2005-09-23 3:03 ` [PATCH 3/4] [PPC32] ibm_emac: " Roland Dreier @ 2005-09-23 3:03 ` Roland Dreier 2005-09-23 3:32 ` Eugene Surovegin 2005-09-23 3:22 ` [PATCH 3/4] [PPC32] ibm_emac: Add 440SPe support Eugene Surovegin 1 sibling, 1 reply; 23+ messages in thread From: Roland Dreier @ 2005-09-23 3:03 UTC (permalink / raw) To: mporter; +Cc: linuxppc-embedded Add support for AMCC PowerPC 440SPe "Yucca" eval board platform. Signed-off-by: Roland Dreier <rolandd@cisco.com> --- arch/ppc/boot/simple/Makefile | 6 + arch/ppc/platforms/4xx/Kconfig | 11 +- arch/ppc/platforms/4xx/Makefile | 1 arch/ppc/platforms/4xx/yucca.c | 286 +++++++++++++++++++++++++++++++++++++++ arch/ppc/platforms/4xx/yucca.h | 115 ++++++++++++++++ include/asm-ppc/ibm4xx.h | 4 + 6 files changed, 421 insertions(+), 2 deletions(-) create mode 100644 arch/ppc/platforms/4xx/yucca.c create mode 100644 arch/ppc/platforms/4xx/yucca.h 542fc1a61c8a721ee4c894ca961d8242d20e813a diff --git a/arch/ppc/boot/simple/Makefile b/arch/ppc/boot/simple/Makefile --- a/arch/ppc/boot/simple/Makefile +++ b/arch/ppc/boot/simple/Makefile @@ -79,6 +79,12 @@ zimageinitrd-$(CONFIG_LUAN) := zImage.i entrypoint-$(CONFIG_LUAN) := 0x01000000 extra.o-$(CONFIG_LUAN) := pibs.o + zimage-$(CONFIG_YUCCA) := zImage-TREE +zimageinitrd-$(CONFIG_YUCCA) := zImage.initrd-TREE + end-$(CONFIG_YUCCA) := yucca + entrypoint-$(CONFIG_YUCCA) := 0x01000000 + extra.o-$(CONFIG_YUCCA) := pibs.o + zimage-$(CONFIG_OCOTEA) := zImage-TREE zimageinitrd-$(CONFIG_OCOTEA) := zImage.initrd-TREE end-$(CONFIG_OCOTEA) := ocotea diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig --- a/arch/ppc/platforms/4xx/Kconfig +++ b/arch/ppc/platforms/4xx/Kconfig @@ -82,6 +82,12 @@ config LUAN help This option enables support for the IBM PPC440SP evaluation board. +config YUCCA + bool "Yucca" + select WANT_EARLY_SERIAL + help + This option enables support for the AMCC PPC440SPe evaluation board. + config OCOTEA bool "Ocotea" select WANT_EARLY_SERIAL @@ -126,7 +132,8 @@ config 440SP config 440SPE bool - default n + depends on YUCCA + default y config 440 bool @@ -162,7 +169,7 @@ config BOOKE config IBM_OCP bool - depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT + depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || YUCCA || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT default y config XILINX_OCP diff --git a/arch/ppc/platforms/4xx/Makefile b/arch/ppc/platforms/4xx/Makefile --- a/arch/ppc/platforms/4xx/Makefile +++ b/arch/ppc/platforms/4xx/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_EBONY) += ebony.o obj-$(CONFIG_EP405) += ep405.o obj-$(CONFIG_BUBINGA) += bubinga.o obj-$(CONFIG_LUAN) += luan.o +obj-$(CONFIG_YUCCA) += yucca.o obj-$(CONFIG_OCOTEA) += ocotea.o obj-$(CONFIG_REDWOOD_5) += redwood5.o obj-$(CONFIG_REDWOOD_6) += redwood6.o diff --git a/arch/ppc/platforms/4xx/yucca.c b/arch/ppc/platforms/4xx/yucca.c new file mode 100644 --- /dev/null +++ b/arch/ppc/platforms/4xx/yucca.c @@ -0,0 +1,286 @@ +/* + * arch/ppc/platforms/4xx/yucca.c + * + * Yucca board specific routines + * + * Roland Dreier <rolandd@cisco.com> (based on yucca.c by Matt Porter) + * + * Copyright 2004-2005 MontaVista Software Inc. + * Copyright (c) 2005 Cisco Systems. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <linux/config.h> +#include <linux/stddef.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/errno.h> +#include <linux/reboot.h> +#include <linux/pci.h> +#include <linux/kdev_t.h> +#include <linux/types.h> +#include <linux/major.h> +#include <linux/blkdev.h> +#include <linux/console.h> +#include <linux/delay.h> +#include <linux/ide.h> +#include <linux/initrd.h> +#include <linux/irq.h> +#include <linux/seq_file.h> +#include <linux/root_dev.h> +#include <linux/tty.h> +#include <linux/serial.h> +#include <linux/serial_core.h> + +#include <asm/system.h> +#include <asm/pgtable.h> +#include <asm/page.h> +#include <asm/dma.h> +#include <asm/io.h> +#include <asm/machdep.h> +#include <asm/ocp.h> +#include <asm/pci-bridge.h> +#include <asm/time.h> +#include <asm/todc.h> +#include <asm/bootinfo.h> +#include <asm/ppc4xx_pic.h> +#include <asm/ppcboot.h> + +#include <syslib/ibm44x_common.h> +#include <syslib/ibm440gx_common.h> +#include <syslib/ibm440sp_common.h> + +/* + * This is a horrible kludge, we eventually need to abstract this + * generic PHY stuff, so the standard phy mode defines can be + * easily used from arch code. + */ +#include "../../../../drivers/net/ibm_emac/ibm_emac_phy.h" + +bd_t __res; + +static struct ibm44x_clocks clocks __initdata; + +static void __init +yucca_calibrate_decr(void) +{ + unsigned int freq; + + if (mfspr(SPRN_CCR1) & CCR1_TCS) + freq = YUCCA_TMR_CLK; + else + freq = clocks.cpu; + + ibm44x_calibrate_decr(freq); +} + +static int +yucca_show_cpuinfo(struct seq_file *m) +{ + seq_printf(m, "vendor\t\t: AMCC\n"); + seq_printf(m, "machine\t\t: PPC440SPe EVB (Yucca)\n"); + + return 0; +} + +static inline int +yucca_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) +{ + struct pci_controller *hose = pci_bus_to_hose(dev->bus->number); + + /* PCIX */ + if (hose->index == 3) { + static char pci_irq_table[][4] = + /* + * PCI IDSEL/INTPIN->INTLINE + * A B C D + */ + { + { 81, -1, -1, -1 }, /* IDSEL 1 - PCIX0 Slot 0 */ + }; + const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4; + return PCI_IRQ_TABLE_LOOKUP; + /* PCIE0 */ + } else if (hose->index == 0) { + static char pci_irq_table[][4] = + /* + * PCI IDSEL/INTPIN->INTLINE + * A B C D + */ + { + { 96, 97, 98, 99 }, + }; + const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4; + return PCI_IRQ_TABLE_LOOKUP; + /* PCIE1 */ + } else if (hose->index == 1) { + static char pci_irq_table[][4] = + /* + * PCI IDSEL/INTPIN->INTLINE + * A B C D + */ + { + { 100, 101, 102, 103 }, + }; + const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4; + return PCI_IRQ_TABLE_LOOKUP; + /* PCIE2 */ + } else if (hose->index == 2) { + static char pci_irq_table[][4] = + /* + * PCI IDSEL/INTPIN->INTLINE + * A B C D + */ + { + { 104, 105, 106, 107 }, + }; + const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4; + return PCI_IRQ_TABLE_LOOKUP; + } + return -1; +} + +static void __init yucca_set_emacdata(void) +{ + struct ocp_def *def; + struct ocp_func_emac_data *emacdata; + + /* Set phy_map, phy_mode, and mac_addr for the EMAC */ + def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0); + emacdata = def->additions; + emacdata->phy_map = 0x00000001; /* Skip 0x00 */ + emacdata->phy_mode = PHY_MODE_GMII; + memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6); +} + +static void __init +yucca_setup_hoses(void) +{ + +} + +TODC_ALLOC(); + +static void __init +yucca_early_serial_map(void) +{ + struct uart_port port; + + /* Setup ioremapped serial port access */ + memset(&port, 0, sizeof(port)); + port.membase = ioremap64(PPC440SPE_UART0_ADDR, 8); + port.irq = UART0_INT; + port.uartclk = clocks.uart0; + port.regshift = 0; + port.iotype = SERIAL_IO_MEM; + port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; + port.line = 0; + + if (early_serial_setup(&port) != 0) { + printk("Early serial init of port 0 failed\n"); + } + + port.membase = ioremap64(PPC440SPE_UART1_ADDR, 8); + port.irq = UART1_INT; + port.uartclk = clocks.uart1; + port.line = 1; + + if (early_serial_setup(&port) != 0) { + printk("Early serial init of port 1 failed\n"); + } + + port.membase = ioremap64(PPC440SPE_UART2_ADDR, 8); + port.irq = UART2_INT; + port.uartclk = BASE_BAUD; + port.line = 2; + + if (early_serial_setup(&port) != 0) { + printk("Early serial init of port 2 failed\n"); + } +} + +static void __init +yucca_setup_arch(void) +{ + yucca_set_emacdata(); + +#if !defined(CONFIG_BDI_SWITCH) + /* + * The Abatron BDI JTAG debugger does not tolerate others + * mucking with the debug registers. + */ + mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM)); +#endif + + /* + * Determine various clocks. + * To be completely correct we should get SysClk + * from FPGA, because it can be changed by on-board switches + * --ebs + */ + /* 440GX and 440SP clocking is the same -mdp */ + ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200); + ocp_sys_info.opb_bus_freq = clocks.opb; + + /* init to some ~sane value until calibrate_delay() runs */ + loops_per_jiffy = 50000000/HZ; + + /* Setup PCIXn host bridges */ + yucca_setup_hoses(); + +#ifdef CONFIG_BLK_DEV_INITRD + if (initrd_start) + ROOT_DEV = Root_RAM0; + else +#endif +#ifdef CONFIG_ROOT_NFS + ROOT_DEV = Root_NFS; +#else + ROOT_DEV = Root_HDA1; +#endif + + yucca_early_serial_map(); + + /* Identify the system */ + printk("Yucca port (Roland Dreier <rolandd@cisco.com>)\n"); +} + +void __init platform_init(unsigned long r3, unsigned long r4, + unsigned long r5, unsigned long r6, unsigned long r7) +{ + parse_bootinfo(find_bootinfo()); + + /* + * If we were passed in a board information, copy it into the + * residual data area. + */ + if (r3) + __res = *(bd_t *)(r3 + KERNELBASE); + +#if defined(CONFIG_BLK_DEV_INITRD) + /* + * If the init RAM disk has been configured in, and there's a valid + * starting address for it, set it up. + */ + if (r4) { + initrd_start = r4 + KERNELBASE; + initrd_end = r5 + KERNELBASE; + } +#endif /* CONFIG_BLK_DEV_INITRD */ + + ibm44x_platform_init(); + + ppc_md.setup_arch = yucca_setup_arch; + ppc_md.show_cpuinfo = yucca_show_cpuinfo; + ppc_md.find_end_of_memory = ibm440sp_find_end_of_memory; + ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */ + + ppc_md.calibrate_decr = yucca_calibrate_decr; +#ifdef CONFIG_KGDB + ppc_md.early_serial_map = yucca_early_serial_map; +#endif +} diff --git a/arch/ppc/platforms/4xx/yucca.h b/arch/ppc/platforms/4xx/yucca.h new file mode 100644 --- /dev/null +++ b/arch/ppc/platforms/4xx/yucca.h @@ -0,0 +1,115 @@ +/* + * arch/ppc/platforms/4xx/yucca.h + * + * Yucca board definitions + * + * Roland Dreier <rolandd@cisco.com> (based on luan.h by Matt Porter) + * + * Copyright 2004-2005 MontaVista Software Inc. + * Copyright (c) 2005 Cisco Systems. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifdef __KERNEL__ +#ifndef __ASM_YUCCA_H__ +#define __ASM_YUCCA_H__ + +#include <linux/config.h> +#include <platforms/4xx/amcc440spe.h> + +/* F/W TLB mapping used in bootloader glue to reset EMAC */ +#define PPC44x_EMAC0_MR0 0xa0000800 + +/* Location of MAC addresses in PIBS image */ +#define PIBS_FLASH_BASE 0xffe00000 +#define PIBS_MAC_BASE (PIBS_FLASH_BASE+0x1b0400) + +/* External timer clock frequency */ +#define YUCCA_TMR_CLK 25000000 + +/* + * FPGA registers + */ +#define YUCCA_FPGA_REG_BASE 0x00000004e2000000ULL +#define YUCCA_FPGA_REG_SIZE 0x24 + +#define FPGA_REG1A 0x1a + +#define FPGA_REG1A_PE0_GLED 0x8000 +#define FPGA_REG1A_PE1_GLED 0x4000 +#define FPGA_REG1A_PE2_GLED 0x2000 +#define FPGA_REG1A_PE0_YLED 0x1000 +#define FPGA_REG1A_PE1_YLED 0x0800 +#define FPGA_REG1A_PE2_YLED 0x0400 +#define FPGA_REG1A_PE0_PWRON 0x0200 +#define FPGA_REG1A_PE1_PWRON 0x0100 +#define FPGA_REG1A_PE2_PWRON 0x0080 +#define FPGA_REG1A_PE0_REFCLK_ENABLE 0x0040 +#define FPGA_REG1A_PE1_REFCLK_ENABLE 0x0020 +#define FPGA_REG1A_PE2_REFCLK_ENABLE 0x0010 +#define FPGA_REG1A_PE_SPREAD0 0x0008 +#define FPGA_REG1A_PE_SPREAD1 0x0004 +#define FPGA_REG1A_PE_SELSOURCE_0 0x0002 +#define FPGA_REG1A_PE_SELSOURCE_1 0x0001 + +#define FPGA_REG1C 0x1c + +#define FPGA_REG1C_PE0_ROOTPOINT 0x8000 +#define FPGA_REG1C_PE1_ENDPOINT 0x4000 +#define FPGA_REG1C_PE2_ENDPOINT 0x2000 +#define FPGA_REG1C_PE0_PRSNT 0x1000 +#define FPGA_REG1C_PE1_PRSNT 0x0800 +#define FPGA_REG1C_PE2_PRSNT 0x0400 +#define FPGA_REG1C_PE0_WAKE 0x0080 +#define FPGA_REG1C_PE1_WAKE 0x0040 +#define FPGA_REG1C_PE2_WAKE 0x0020 +#define FPGA_REG1C_PE0_PERST 0x0010 +#define FPGA_REG1C_PE1_PERST 0x0008 +#define FPGA_REG1C_PE2_PERST 0x0004 + +/* + * Serial port defines + */ +#define RS_TABLE_SIZE 3 + +/* PIBS defined UART mappings, used before early_serial_setup */ +#define UART0_IO_BASE 0xa0000200 +#define UART1_IO_BASE 0xa0000300 +#define UART2_IO_BASE 0xa0000600 + +#define BASE_BAUD 11059200 +#define STD_UART_OP(num) \ + { 0, BASE_BAUD, 0, UART##num##_INT, \ + (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ + iomem_base: UART##num##_IO_BASE, \ + io_type: SERIAL_IO_MEM}, + +#define SERIAL_PORT_DFNS \ + STD_UART_OP(0) \ + STD_UART_OP(1) \ + STD_UART_OP(2) + +/* PCI support */ +#define YUCCA_PCIX_LOWER_IO 0x00000000 +#define YUCCA_PCIX_UPPER_IO 0x0000ffff +#define YUCCA_PCIX_LOWER_MEM 0x80000000 +#define YUCCA_PCIX_UPPER_MEM 0x8fffffff +#define YUCCA_PCIE0_LOWER_MEM 0x90000000 +#define YUCCA_PCIE0_UPPER_MEM 0x9fffffff +#define YUCCA_PCIE1_LOWER_MEM 0xa0000000 +#define YUCCA_PCIE1_UPPER_MEM 0xafffffff +#define YUCCA_PCIE2_LOWER_MEM 0xb0000000 +#define YUCCA_PCIE2_UPPER_MEM 0xbfffffff + +#define YUCCA_PCIX_MEM_SIZE 0x10000000 +#define YUCCA_PCIX_MEM_OFFSET 0x00000000 +#define YUCCA_PCIE_MEM_SIZE 0x10000000 +#define YUCCA_PCIE_MEM_OFFSET 0x00000000 + +#endif /* __ASM_YUCCA_H__ */ +#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/ibm4xx.h b/include/asm-ppc/ibm4xx.h --- a/include/asm-ppc/ibm4xx.h +++ b/include/asm-ppc/ibm4xx.h @@ -97,6 +97,10 @@ void ppc4xx_init(unsigned long r3, unsig #include <platforms/4xx/luan.h> #endif +#if defined(CONFIG_YUCCA) +#include <platforms/4xx/yucca.h> +#endif + #if defined(CONFIG_OCOTEA) #include <platforms/4xx/ocotea.h> #endif ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 4/4] [PPC32] Add Yucca (440SPe eval board) platform 2005-09-23 3:03 ` [PATCH 4/4] [PPC32] Add Yucca (440SPe eval board) platform Roland Dreier @ 2005-09-23 3:32 ` Eugene Surovegin 2005-09-23 5:44 ` Roland Dreier 0 siblings, 1 reply; 23+ messages in thread From: Eugene Surovegin @ 2005-09-23 3:32 UTC (permalink / raw) To: Roland Dreier; +Cc: linuxppc-embedded On Thu, Sep 22, 2005 at 08:03:35PM -0700, Roland Dreier wrote: > Add support for AMCC PowerPC 440SPe "Yucca" eval board platform. [snip] > +/* > + * This is a horrible kludge, we eventually need to abstract this > + * generic PHY stuff, so the standard phy mode defines can be > + * easily used from arch code. > + */ > +#include "../../../../drivers/net/ibm_emac/ibm_emac_phy.h" This is not needed anymore. Please, remove this. -- Eugene ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 4/4] [PPC32] Add Yucca (440SPe eval board) platform 2005-09-23 3:32 ` Eugene Surovegin @ 2005-09-23 5:44 ` Roland Dreier 0 siblings, 0 replies; 23+ messages in thread From: Roland Dreier @ 2005-09-23 5:44 UTC (permalink / raw) To: mporter; +Cc: linuxppc-embedded Eugene> This is not needed anymore. Please, remove this. Done and also pushed out in the new git tree. - R. ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 3/4] [PPC32] ibm_emac: Add 440SPe support 2005-09-23 3:03 ` [PATCH 3/4] [PPC32] ibm_emac: " Roland Dreier 2005-09-23 3:03 ` [PATCH 4/4] [PPC32] Add Yucca (440SPe eval board) platform Roland Dreier @ 2005-09-23 3:22 ` Eugene Surovegin 2005-09-23 5:25 ` Roland Dreier 1 sibling, 1 reply; 23+ messages in thread From: Eugene Surovegin @ 2005-09-23 3:22 UTC (permalink / raw) To: Roland Dreier; +Cc: linuxppc-embedded On Thu, Sep 22, 2005 at 08:03:35PM -0700, Roland Dreier wrote: > Eugene, I'm not sure what the status of your ibm_emac rewrite is. Is > there a tree somewhere that you would like me to merge this change > with and then send you a patch, or do you want to take care of merging? Well, new driver was sent to jgarzik and netdev list three weeks ago. So far I haven't heard anything technical from Jeff. I don't know when and even if it will be merged. There is a GIT tree with new driver, for more info look at http://kernel.ebshome.net/emac/index.html I don't know what to recommend now - wait for net driver maintainer (I've heard some people have been waiting for couple months already) or sent this patch upstream ignoring new driver :(. Matt? I'll try to look at merging your patch into my tree, but probably not right now - I'm kinda busy with other stuff and netdev "progress" doesn't quite motivate me working on this project, frankly. Though, if you can send me a patch against my tree, I'll appreciate it :). -- Eugene ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 3/4] [PPC32] ibm_emac: Add 440SPe support 2005-09-23 3:22 ` [PATCH 3/4] [PPC32] ibm_emac: Add 440SPe support Eugene Surovegin @ 2005-09-23 5:25 ` Roland Dreier 2005-09-23 8:24 ` Eugene Surovegin 2005-09-23 17:11 ` Matt Porter 0 siblings, 2 replies; 23+ messages in thread From: Roland Dreier @ 2005-09-23 5:25 UTC (permalink / raw) To: Eugene Surovegin; +Cc: linuxppc-embedded Eugene> Well, new driver was sent to jgarzik and netdev list three Eugene> weeks ago. So far I haven't heard anything technical from Eugene> Jeff. I don't know when and even if it will be merged. Assuming everyone in the PPC4xx world thinks your driver should replace the old driver, it might be worth sending directly to Andrew. There's no reason Jeff has to become a bottleneck for this. Eugene> I'll try to look at merging your patch into my tree, but Eugene> probably not right now - I'm kinda busy with other stuff Eugene> and netdev "progress" doesn't quite motivate me working on Eugene> this project, frankly. Though, if you can send me a patch Eugene> against my tree, I'll appreciate it :). No problem at all. Here's a patch against your git tree -- only tested on my Yucca board, so you might want to doublecheck that I didn't break all the systems will the opposite polarity. Thanks, Roland For some reason, the hardware designers made the polarity of one bit in the 440SPe's PHY interface register the opposite of all other PPC 440 chips. To handle this, abstract our access to this bit and do the right thing based on the configured CPU type. Signed-off-by: Roland Dreier <rolandd@cisco.com> diff --git a/drivers/net/ibm_emac/ibm_emac.h b/drivers/net/ibm_emac/ibm_emac.h --- a/drivers/net/ibm_emac/ibm_emac.h +++ b/drivers/net/ibm_emac/ibm_emac.h @@ -26,7 +26,7 @@ /* This is a simple check to prevent use of this driver on non-tested SoCs */ #if !defined(CONFIG_405GP) && !defined(CONFIG_405GPR) && !defined(CONFIG_405EP) && \ !defined(CONFIG_440GP) && !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && \ - !defined(CONFIG_440EP) && !defined(CONFIG_NP405H) + !defined(CONFIG_440EP) && !defined(CONFIG_NP405H) && !defined(CONFIG_440SPE) #error "Unknown SoC. Please, check chip user manual and make sure EMAC defines are OK" #endif diff --git a/drivers/net/ibm_emac/ibm_emac_core.c b/drivers/net/ibm_emac/ibm_emac_core.c --- a/drivers/net/ibm_emac/ibm_emac_core.c +++ b/drivers/net/ibm_emac/ibm_emac_core.c @@ -139,6 +139,29 @@ static inline void EMAC_RX_CLK_DEFAULT(i #define EMAC_CLK_EXTERNAL ((void)0) #endif +/* + * For the 440SPe, AMCC inexplicably changed the polarity of + * the "operation complete" bit in the MII control register. + */ +#ifdef CONFIG_440SPE +static inline int emac_phy_done(uint32_t stacr) +{ + return !(stacr & EMAC_STACR_OC); +}; + +#define EMAC_STACR_START EMAC_STACR_OC + +#else /* CONFIG_440SPE */ + +static inline int emac_phy_done(uint32_t stacr) +{ + return stacr & EMAC_STACR_OC; +}; + +#define EMAC_STACR_START 0 +#endif /* CONFIG_440SPE */ + + /* I don't want to litter system log with timeout errors * when we have brain-damaged PHY. */ @@ -546,7 +569,7 @@ static int __emac_mdio_read(struct ocp_e /* Wait for management interface to become idle */ n = 10; - while (!(in_be32(&p->stacr) & EMAC_STACR_OC)) { + while (!emac_phy_done(in_be32(&p->stacr))) { udelay(1); if (!--n) goto to; @@ -556,11 +579,12 @@ static int __emac_mdio_read(struct ocp_e out_be32(&p->stacr, EMAC_STACR_BASE(emac_opb_mhz()) | EMAC_STACR_STAC_READ | (reg & EMAC_STACR_PRA_MASK) - | ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT)); + | ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT) + | EMAC_STACR_START); /* Wait for read to complete */ n = 100; - while (!((r = in_be32(&p->stacr)) & EMAC_STACR_OC)) { + while (!emac_phy_done(r = in_be32(&p->stacr))) { udelay(1); if (!--n) goto to; @@ -594,7 +618,7 @@ static void __emac_mdio_write(struct ocp /* Wait for management interface to be idle */ n = 10; - while (!(in_be32(&p->stacr) & EMAC_STACR_OC)) { + while (!emac_phy_done(in_be32(&p->stacr))) { udelay(1); if (!--n) goto to; @@ -605,11 +629,12 @@ static void __emac_mdio_write(struct ocp EMAC_STACR_BASE(emac_opb_mhz()) | EMAC_STACR_STAC_WRITE | (reg & EMAC_STACR_PRA_MASK) | ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT) | - (val << EMAC_STACR_PHYD_SHIFT)); + (val << EMAC_STACR_PHYD_SHIFT) | + EMAC_STACR_START); /* Wait for write to complete */ n = 100; - while (!(in_be32(&p->stacr) & EMAC_STACR_OC)) { + while (!emac_phy_done(in_be32(&p->stacr))) { udelay(1); if (!--n) goto to; diff --git a/drivers/net/ibm_emac/ibm_emac_mal.h b/drivers/net/ibm_emac/ibm_emac_mal.h --- a/drivers/net/ibm_emac/ibm_emac_mal.h +++ b/drivers/net/ibm_emac/ibm_emac_mal.h @@ -34,7 +34,8 @@ #if defined(CONFIG_405GP) || defined(CONFIG_405GPR) || defined(CONFIG_405EP) || \ defined(CONFIG_440EP) || defined(CONFIG_NP405H) #define MAL_VERSION 1 -#elif defined(CONFIG_440GP) || defined(CONFIG_440GX) || defined(CONFIG_440SP) +#elif defined(CONFIG_440GP) || defined(CONFIG_440GX) || defined(CONFIG_440SP) || \ + defined(CONFIG_440SPE) #define MAL_VERSION 2 #else #error "Unknown SoC, please check chip manual and choose MAL 'version'" ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 3/4] [PPC32] ibm_emac: Add 440SPe support 2005-09-23 5:25 ` Roland Dreier @ 2005-09-23 8:24 ` Eugene Surovegin 2005-09-23 15:17 ` Roland Dreier 2005-09-23 17:11 ` Matt Porter 1 sibling, 1 reply; 23+ messages in thread From: Eugene Surovegin @ 2005-09-23 8:24 UTC (permalink / raw) To: Roland Dreier; +Cc: linuxppc-embedded On Thu, Sep 22, 2005 at 10:25:26PM -0700, Roland Dreier wrote: > No problem at all. Here's a patch against your git tree -- only > tested on my Yucca board, so you might want to doublecheck that I > didn't break all the systems will the opposite polarity. Thanks Roland, I've just pushed your patch with minor style changes to my GIT tree. I changed uint32_t -> u32 and moved emac_phy_done() functions to ibm_emac.h. Booted new kernel on Ocotea and everything seems to be OK. -- Eugene ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 3/4] [PPC32] ibm_emac: Add 440SPe support 2005-09-23 8:24 ` Eugene Surovegin @ 2005-09-23 15:17 ` Roland Dreier 0 siblings, 0 replies; 23+ messages in thread From: Roland Dreier @ 2005-09-23 15:17 UTC (permalink / raw) To: mporter; +Cc: linuxppc-embedded Eugene> Booted new kernel on Ocotea and everything seems to be OK. I tested on Yucca/440SPe and it works fine for me too. Thanks, Roland ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 3/4] [PPC32] ibm_emac: Add 440SPe support 2005-09-23 5:25 ` Roland Dreier 2005-09-23 8:24 ` Eugene Surovegin @ 2005-09-23 17:11 ` Matt Porter 2005-09-23 20:25 ` Roland Dreier 1 sibling, 1 reply; 23+ messages in thread From: Matt Porter @ 2005-09-23 17:11 UTC (permalink / raw) To: Roland Dreier; +Cc: linuxppc-embedded On Thu, Sep 22, 2005 at 10:25:26PM -0700, Roland Dreier wrote: > Eugene> Well, new driver was sent to jgarzik and netdev list three > Eugene> weeks ago. So far I haven't heard anything technical from > Eugene> Jeff. I don't know when and even if it will be merged. > > Assuming everyone in the PPC4xx world thinks your driver should > replace the old driver, it might be worth sending directly to Andrew. > There's no reason Jeff has to become a bottleneck for this. We're working on this. It's not exactly that simple since Jeff established that all net drivers must enter through the netdev tree. I expect it can get merged post 2.6.14 if all goes well. -Matt ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 3/4] [PPC32] ibm_emac: Add 440SPe support 2005-09-23 17:11 ` Matt Porter @ 2005-09-23 20:25 ` Roland Dreier 2005-09-23 20:36 ` Matt Porter 0 siblings, 1 reply; 23+ messages in thread From: Roland Dreier @ 2005-09-23 20:25 UTC (permalink / raw) To: Matt Porter; +Cc: linuxppc-embedded Matt> We're working on this. It's not exactly that simple since Matt> Jeff established that all net drivers must enter through the Matt> netdev tree. I expect it can get merged post 2.6.14 if all Matt> goes well. Jeff may want all net drivers to go through his tree, but with all due respect to him, there's no law that says it has to be so. cf. Linus's recent post: http://lkml.org/lkml/2005/9/22/220 - R. ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 3/4] [PPC32] ibm_emac: Add 440SPe support 2005-09-23 20:25 ` Roland Dreier @ 2005-09-23 20:36 ` Matt Porter 0 siblings, 0 replies; 23+ messages in thread From: Matt Porter @ 2005-09-23 20:36 UTC (permalink / raw) To: Roland Dreier; +Cc: linuxppc-embedded On Fri, Sep 23, 2005 at 01:25:09PM -0700, Roland Dreier wrote: > Matt> We're working on this. It's not exactly that simple since > Matt> Jeff established that all net drivers must enter through the > Matt> netdev tree. I expect it can get merged post 2.6.14 if all > Matt> goes well. > > Jeff may want all net drivers to go through his tree, but with all due > respect to him, there's no law that says it has to be so. > > cf. Linus's recent post: http://lkml.org/lkml/2005/9/22/220 Yep, one step at a time. There's no rush for today or tomorrow... nothing like this is going into the tree until post 2.6.14 anyway. -Matt ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/4] [PPC32] Add 440SPe support 2005-09-23 3:03 ` [PATCH 2/4] [PPC32] Add 440SPe support Roland Dreier 2005-09-23 3:03 ` [PATCH 3/4] [PPC32] ibm_emac: " Roland Dreier @ 2005-09-23 3:29 ` Eugene Surovegin 2005-09-23 5:44 ` Roland Dreier 2005-09-23 17:20 ` Matt Porter 2 siblings, 1 reply; 23+ messages in thread From: Eugene Surovegin @ 2005-09-23 3:29 UTC (permalink / raw) To: Roland Dreier; +Cc: linuxppc-embedded On Thu, Sep 22, 2005 at 08:03:35PM -0700, Roland Dreier wrote: > Add support for the AMCC PowerPC 440SPe SoC. [snip] > +static struct ocp_func_mal_data amc440spe_mal0_def = { > + .num_tx_chans = 1, /* Number of TX channels */ > + .num_rx_chans = 1, /* Number of RX channels */ > + .txeob_irq = 38, /* TX End Of Buffer IRQ */ > + .rxeob_irq = 39, /* RX End Of Buffer IRQ */ > + .txde_irq = 34, /* TX Descriptor Error IRQ */ > + .rxde_irq = 35, /* RX Descriptor Error IRQ */ > + .serr_irq = 33, /* MAL System Error IRQ */ > +}; > +OCP_SYSFS_MAL_DATA() Roland, I recently added new field (.dcr_base) to this structure (as a preparation step for new EMAC driver), could you do this for 440SPe as well? It's not needed right now, but as soon as new EMAC driver is in, 440SPe will stop working. [snip] > +static void __init ppc4xx_pic_impl_init(void) > +{ > + /* Enable cascade interrupts in UIC0 */ > + /* Enable cascade interrupt in UIC0 */ I think you probably missed this part :) -- Eugene ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/4] [PPC32] Add 440SPe support 2005-09-23 3:29 ` [PATCH 2/4] [PPC32] " Eugene Surovegin @ 2005-09-23 5:44 ` Roland Dreier 2005-09-23 17:17 ` Matt Porter 0 siblings, 1 reply; 23+ messages in thread From: Roland Dreier @ 2005-09-23 5:44 UTC (permalink / raw) To: mporter; +Cc: linuxppc-embedded Eugene> Roland, I recently added new field (.dcr_base) to this Eugene> structure (as a preparation step for new EMAC driver), Eugene> could you do this for 440SPe as well? It's not needed Eugene> right now, but as soon as new EMAC driver is in, 440SPe Eugene> will stop working. Eugene> I think you probably missed this part :) Both fixed and pushed in a new git tree... - R. ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/4] [PPC32] Add 440SPe support 2005-09-23 5:44 ` Roland Dreier @ 2005-09-23 17:17 ` Matt Porter 2005-09-23 20:27 ` Roland Dreier 0 siblings, 1 reply; 23+ messages in thread From: Matt Porter @ 2005-09-23 17:17 UTC (permalink / raw) To: Roland Dreier; +Cc: linuxppc-embedded On Thu, Sep 22, 2005 at 10:44:35PM -0700, Roland Dreier wrote: > Eugene> Roland, I recently added new field (.dcr_base) to this > Eugene> structure (as a preparation step for new EMAC driver), > Eugene> could you do this for 440SPe as well? It's not needed > Eugene> right now, but as soon as new EMAC driver is in, 440SPe > Eugene> will stop working. > > Eugene> I think you probably missed this part :) > > Both fixed and pushed in a new git tree... Can you rebase off of Eugene's tree and resend patches? For the moment the new EMAC driver is the lynchpin in anything new PPC4xx. I want to hold off merging anything that involves current EMAC driver changes until the new driver is in. In any case, nothing like this can go upstream until after 2.6.14 is released. We are expecting the new EMAC driver to be merged at that point. If you have this stuff rebased from his tree we can easily merge them post-EMAC merge. -Matt ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/4] [PPC32] Add 440SPe support 2005-09-23 17:17 ` Matt Porter @ 2005-09-23 20:27 ` Roland Dreier 0 siblings, 0 replies; 23+ messages in thread From: Roland Dreier @ 2005-09-23 20:27 UTC (permalink / raw) To: Matt Porter; +Cc: linuxppc-embedded Matt> Can you rebase off of Eugene's tree and resend patches? For Matt> the moment the new EMAC driver is the lynchpin in anything Matt> new PPC4xx. I want to hold off merging anything that Matt> involves current EMAC driver changes until the new driver is Matt> in. In any case, nothing like this can go upstream until Matt> after 2.6.14 is released. We are expecting the new EMAC Matt> driver to be merged at that point. If you have this stuff Matt> rebased from his tree we can easily merge them post-EMAC Matt> merge. I've already sent patches to Eugene that are in his EMAC tree. So his driver will support 440SPe and can be merged before or after my patches. If it's before then just dump my ibm_emac patch on the floor. - R. ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/4] [PPC32] Add 440SPe support 2005-09-23 3:03 ` [PATCH 2/4] [PPC32] Add 440SPe support Roland Dreier 2005-09-23 3:03 ` [PATCH 3/4] [PPC32] ibm_emac: " Roland Dreier 2005-09-23 3:29 ` [PATCH 2/4] [PPC32] " Eugene Surovegin @ 2005-09-23 17:20 ` Matt Porter 2005-09-23 20:27 ` Roland Dreier 2005-09-23 22:44 ` Roland Dreier 2 siblings, 2 replies; 23+ messages in thread From: Matt Porter @ 2005-09-23 17:20 UTC (permalink / raw) To: Roland Dreier; +Cc: linuxppc-embedded On Thu, Sep 22, 2005 at 08:03:35PM -0700, Roland Dreier wrote: > Add support for the AMCC PowerPC 440SPe SoC. > > Signed-off-by: Roland Dreier <rolandd@cisco.com> > > --- > > arch/ppc/kernel/cputable.c | 10 +++ > arch/ppc/platforms/4xx/Kconfig | 8 ++ > arch/ppc/platforms/4xx/Makefile | 1 > arch/ppc/platforms/4xx/amcc440spe.c | 134 +++++++++++++++++++++++++++++++++++ > arch/ppc/platforms/4xx/amcc440spe.h | 64 +++++++++++++++++ Please change these new files to ppc440spe.*. After the new EMAC driver is merged, we are planning a Great Renaming(tm) to make the current filenames be vendor neutral. i.e. ibm4*->ppc4* -Matt ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/4] [PPC32] Add 440SPe support 2005-09-23 17:20 ` Matt Porter @ 2005-09-23 20:27 ` Roland Dreier 2005-09-23 22:44 ` Roland Dreier 1 sibling, 0 replies; 23+ messages in thread From: Roland Dreier @ 2005-09-23 20:27 UTC (permalink / raw) To: Matt Porter; +Cc: linuxppc-embedded Matt> Please change these new files to ppc440spe.*. After the new Matt> EMAC driver is merged, we are planning a Great Renaming(tm) Matt> to make the current filenames be vendor neutral. i.e. ibm4*->ppc4* Okey-doke, will do. - R. ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/4] [PPC32] Add 440SPe support 2005-09-23 17:20 ` Matt Porter 2005-09-23 20:27 ` Roland Dreier @ 2005-09-23 22:44 ` Roland Dreier 2005-09-23 22:58 ` Eugene Surovegin 1 sibling, 1 reply; 23+ messages in thread From: Roland Dreier @ 2005-09-23 22:44 UTC (permalink / raw) To: Matt Porter; +Cc: linuxppc-embedded Matt> Please change these new files to ppc440spe.*. After the new Matt> EMAC driver is merged, we are planning a Great Renaming(tm) Matt> to make the current filenames be vendor neutral. i.e. ibm4*->ppc4* OK, I made these changes and rebased to Eugene's EMAC git tree. This tree passes some basic tests on my Yucca board. I just pushed this, so pending mirror delays, it will be at rsync://rsync.kernel.org/pub/scm/linux/kernel/git/roland/ppc440spe.git I can repost the patchset if anyone wants to see it. BTW, Eugene, you might want to do a 'git prune-packed' on your git tree. It's pretty wasteful to clone your tree now, because you have a lot of individual objects that also appear in Linus's packs. - R. ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 2/4] [PPC32] Add 440SPe support 2005-09-23 22:44 ` Roland Dreier @ 2005-09-23 22:58 ` Eugene Surovegin 0 siblings, 0 replies; 23+ messages in thread From: Eugene Surovegin @ 2005-09-23 22:58 UTC (permalink / raw) To: Roland Dreier; +Cc: linuxppc-embedded On Fri, Sep 23, 2005 at 03:44:35PM -0700, Roland Dreier wrote: > BTW, Eugene, you might want to do a 'git prune-packed' on your git > tree. It's pretty wasteful to clone your tree now, because you have a > lot of individual objects that also appear in Linus's packs. Yeah, I did this yesterday, so I guess your next pulls should be OK. You may need to do this on the cloned tree as well. -- Eugene ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 0/4] updated 440SPe support
@ 2005-10-12 4:20 Roland Dreier
2005-10-12 4:20 ` [PATCH 1/4] [PPC32] Allow ERPN for early serial to depend on CPU type Roland Dreier
0 siblings, 1 reply; 23+ messages in thread
From: Roland Dreier @ 2005-10-12 4:20 UTC (permalink / raw)
To: mporter; +Cc: linuxppc-embedded
Here is an updated series of patches that add basic support for AMCC's
PowerPC 440SPe SoC. With these patches, the kernel will boot and run
on the "Yucca" 440SPe eval board, with ethernet, serial and PCI
Express in root port mode working (tested with an InfiniBand HCA,
naturally ;).
Since my last posting, I've fixed a few bugs (UIC3 interrupt handling
being the most notable fix) and implemented basic PCI Express support.
I left out the changes required for the old ibm_emac ethernet driver,
since I'm assuming Eugene's new driver will be merged, and his tree
already has 440SPe support.
I now have all the features I need for the project I'm working on, so
I don't expect to be adding much to my port. I will do whatever
cleanup, bugfixing and integration is required to get this merged
upstream. It looks like 2.6.15 will be opening up soon, so please let
me know if there's anything I can do to make merging easier.
I also have a git tree based on Eugene Surovegin's git tree at
rsync://rsync.kernel.org/pub/scm/linux/kernel/git/roland/ppc440spe.git
that contains all of these patches, in case that makes it easier to
merge this stuff.
Thanks,
Roland
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH 1/4] [PPC32] Allow ERPN for early serial to depend on CPU type 2005-10-12 4:20 [PATCH 0/4] updated " Roland Dreier @ 2005-10-12 4:20 ` Roland Dreier 0 siblings, 0 replies; 23+ messages in thread From: Roland Dreier @ 2005-10-12 4:20 UTC (permalink / raw) To: mporter; +Cc: linuxppc-embedded The PowerPC 440SPe supports up to 16 GB of RAM, and therefore its IO registers are at 0x4_xxxx_xxxx instead of being at 0x1_xxxx_xxxx like most other PPC 440 chips. To allow for this, this patch moves the definition of the ERPN used for mapping UART0 from being hard-coded in the head_44x.S assembly code to being defined in ibm44x.h. Signed-off-by: Roland Dreier <rolandd@cisco.com> --- arch/ppc/kernel/head_44x.S | 4 ++-- include/asm-ppc/ibm44x.h | 7 ++++++- 2 files changed, 8 insertions(+), 3 deletions(-) applies-to: 191b41b19d91b0893c5699fa3ff5ca984841b7a7 00f2126e653cc45212ae72aa0cac150eff712087 diff --git a/arch/ppc/kernel/head_44x.S b/arch/ppc/kernel/head_44x.S index 599245b..92bf8ab 100644 --- a/arch/ppc/kernel/head_44x.S +++ b/arch/ppc/kernel/head_44x.S @@ -190,8 +190,8 @@ skpinv: addi r4,r4,1 /* Increment */ /* xlat fields */ lis r4,UART0_PHYS_IO_BASE@h /* RPN depends on SoC */ -#ifndef CONFIG_440EP - ori r4,r4,0x0001 /* ERPN is 1 for second 4GB page */ +#ifdef UART0_PHYS_ERPN + ori r4,r4,UART0_PHYS_ERPN /* Add ERPN if above 4GB */ #endif /* attrib fields */ diff --git a/include/asm-ppc/ibm44x.h b/include/asm-ppc/ibm44x.h index e5374be..197a9ff 100644 --- a/include/asm-ppc/ibm44x.h +++ b/include/asm-ppc/ibm44x.h @@ -34,12 +34,17 @@ /* Lowest TLB slot consumed by the default pinned TLBs */ #define PPC44x_LOW_SLOT 63 -/* LS 32-bits of UART0 physical address location for early serial text debug */ +/* + * Least significant 32-bits and extended real page number (ERPN) of + * UART0 physical address location for early serial text debug + */ #if defined(CONFIG_440SP) +#define UART0_PHYS_ERPN 1 #define UART0_PHYS_IO_BASE 0xf0000200 #elif defined(CONFIG_440EP) #define UART0_PHYS_IO_BASE 0xe0000000 #else +#define UART0_PHYS_ERPN 1 #define UART0_PHYS_IO_BASE 0x40000200 #endif --- 0.99.8.GIT ^ permalink raw reply related [flat|nested] 23+ messages in thread
end of thread, other threads:[~2005-10-12 4:20 UTC | newest] Thread overview: 23+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2005-09-23 3:03 [PATCH 0/4] 440SPe support Roland Dreier 2005-09-23 3:03 ` [PATCH 1/4] [PPC32] Allow ERPN for early serial to depend on CPU type Roland Dreier 2005-09-23 3:03 ` [PATCH 2/4] [PPC32] Add 440SPe support Roland Dreier 2005-09-23 3:03 ` [PATCH 3/4] [PPC32] ibm_emac: " Roland Dreier 2005-09-23 3:03 ` [PATCH 4/4] [PPC32] Add Yucca (440SPe eval board) platform Roland Dreier 2005-09-23 3:32 ` Eugene Surovegin 2005-09-23 5:44 ` Roland Dreier 2005-09-23 3:22 ` [PATCH 3/4] [PPC32] ibm_emac: Add 440SPe support Eugene Surovegin 2005-09-23 5:25 ` Roland Dreier 2005-09-23 8:24 ` Eugene Surovegin 2005-09-23 15:17 ` Roland Dreier 2005-09-23 17:11 ` Matt Porter 2005-09-23 20:25 ` Roland Dreier 2005-09-23 20:36 ` Matt Porter 2005-09-23 3:29 ` [PATCH 2/4] [PPC32] " Eugene Surovegin 2005-09-23 5:44 ` Roland Dreier 2005-09-23 17:17 ` Matt Porter 2005-09-23 20:27 ` Roland Dreier 2005-09-23 17:20 ` Matt Porter 2005-09-23 20:27 ` Roland Dreier 2005-09-23 22:44 ` Roland Dreier 2005-09-23 22:58 ` Eugene Surovegin -- strict thread matches above, loose matches on Subject: below -- 2005-10-12 4:20 [PATCH 0/4] updated " Roland Dreier 2005-10-12 4:20 ` [PATCH 1/4] [PPC32] Allow ERPN for early serial to depend on CPU type Roland Dreier
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