From: Eugene Surovegin <ebs@ebshome.net>
To: Ed Goforth <egoforth@gmail.com>
Cc: linuxppc-embedded@ozlabs.org
Subject: Re: 440gx GPIO
Date: Mon, 13 Feb 2006 22:59:34 -0800 [thread overview]
Message-ID: <20060214065934.GA12465@gate.ebshome.net> (raw)
In-Reply-To: <43F168A3.4020808@gmail.com>
On Tue, Feb 14, 2006 at 12:20:35AM -0500, Ed Goforth wrote:
> I am struggling with a problem and I hope someone can give me some
> pointers. We have a custom board with a 440gx. I need to drive GPIO11
> low. The best as I can tell from the docs, I need to set bit 11 of the
> TCR to 1 and bit 11 of the OR to 0 to do this.
Check that this pin is enabled as GPIO not as a function pin
(SDR0_PFC0 register).
Also, just to be sure that you remapped GPIO registers correctly, use
ioremap64 with full physical address (not just low 32 bits).
--
Eugene
next prev parent reply other threads:[~2006-02-14 6:59 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-02-14 5:20 440gx GPIO Ed Goforth
2006-02-14 6:59 ` Eugene Surovegin [this message]
2006-02-14 13:48 ` Ed Goforth
2006-02-14 17:01 ` Eugene Surovegin
2006-02-14 17:10 ` Ed Goforth
2006-02-14 21:47 ` Ed Goforth
2006-02-20 17:20 ` Ed Goforth
-- strict thread matches above, loose matches on Subject: below --
2006-02-15 0:01 Howard, Marc
2006-02-20 17:13 ` Ed Goforth
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