From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gateway-1237.mvista.com (gateway-1237.mvista.com [63.81.120.158]) by ozlabs.org (Postfix) with ESMTP id 9449F67AC5 for ; Wed, 31 May 2006 04:25:34 +1000 (EST) Date: Tue, 30 May 2006 11:27:46 -0700 From: "Mark A. Greer" To: Roger Larsson Subject: Re: Setting I&D cache enable in the same mtspr instruction Message-ID: <20060530182746.GA26830@mag.az.mvista.com> References: <200605291415.14908.roger.larsson@norran.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii In-Reply-To: <200605291415.14908.roger.larsson@norran.net> Cc: linuxppc-embedded@ozlabs.org List-Id: Linux on Embedded PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Mon, May 29, 2006 at 02:15:14PM +0200, Roger Larsson wrote: > Is the patch reversed? Sure looks like it. > diff -Naur old new > patch > > And what about comments, are they all still valid? > "enable and invalidate caches" is now only Data cache... > > In cases when I am writing code like this I try to > include the reason why it is not "optimized" together > in one write... (or soon someone will do that optimization). Good point. > /RogerL Also, please send the patches *inline*. Mark