From: Om Vadlapatla <pdfdoc15@yahoo.com>
To: "linuxppc-embedded@ozlabs.org" <linuxppc-embedded@ozlabs.org>,
"U-Boot-Users@lists.sourceforge.net"
<U-Boot-Users@lists.sourceforge.net>
Subject: board initialization problem
Date: Wed, 14 Jun 2006 09:40:23 -0700 (PDT) [thread overview]
Message-ID: <20060614164023.83004.qmail@web37109.mail.mud.yahoo.com> (raw)
[-- Attachment #1: Type: text/plain, Size: 2344 bytes --]
K0: Original Montavista kernel
K1: Kernel without D-cache Adapted for 4x60(SDH 2/6
ch)
K2: Kernel with D-cache enabled for 4160 (SDH 6 ch)
Difference between K1 & K2:
1. D-cache (~/kernel2.4.17/arch/ppc/kernel/head.S)
here only one line difference.
2. Page table & cache buffer allocation
(~/kernel2.4.17/arch/ppc/8260_io/comproc.c)
I can send the difference only 4 lines only setting
the buffer arrays.
Target: 4160 (compat SDH unit)
Abatron: Jtag Debugger
fw4x60.cfg: old config file for Abatron
fw8270.cfg: new config file for Abatron
The tests tried using U-BOOT:
1. Loaded K1 onto target independent of Abatron
2. Loaded K2 onto target with Abatron fw8270.cfg
ran busy looptest for K1 & K2 result: K2 40 times
faster
3. Tried to load K2 to target without Abatron result:
Failed
Conclusions & comments:
There are significant differences between fw4x60.cfg &
fw8270.cfg.
These differences need to be incorporated in the new
Kernel (OR I am not sure about it but may be into the
Boot-loader).
Core Initialization file in kernel:
~/kernel2.4.17/arch/ppc/kernel/head.S
Speculated changes:
~/kernel2.4.17/arch/ppc/8260_io/comproc.c
It was speculated that the cached buffers triggered
the exception. And commproc.c was modified to make
those buffers uncacheable. But that made things worse:
invalidate_dcache_range() and flush_tlb_page() cause
another exception to occur (not identified).
U-boot initialization files:
~/u-boot/cpu/mpc8260
start.S, cpu_init.c
Both these files in u-boot are meant to initialize
the core & MMU.
If the config changes need to go into the kernel I am
not sure if it is the head.S file.
If the config changes need to go into the boot loader
I am not sure while the kernel opperates if there will
be any unpredictable behaviour.
Irrespective of where the changes go, the main task is
to analize each difference between fw4x60.cfg &
fw8270.cfg and develope the initialization code.
If any one has another plan of action please let me
know, I appreciate guidance.
Attached are the two config files.
Sincerely,
Om Vadlapatla
PS:- All I need is to load the new kernel with out a
glitch coz I can do it with the Abatron pluged in.
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[-- Attachment #2: 1384370366-fw4x60.cfg.txt --]
[-- Type: text/plain, Size: 5839 bytes --]
; -----------------------------------------------------------------------------
; Abatron bdiGDB configuration file for the FW4X60 platform
; single board computer running MontaVista Linux.
;
; The physical memory map is as follows:
; 0x00000000 - 0x0FFFFFFF 256MB 60x SDRAM on CS1 and CS2
; 0x30000000 - 0x33FFFFFF 64MB local SDRAM on CS5
; 0x40000000 - 0x41FFFFFF 32MB FPGA on CS6
; 0x50000000 - 0x50FFFFFF 16MB RTC on CS7
; 0x80000000 - 0x80007FFF 32KB IDE on CS9
; 0xF0000000 - 0xF001FFFF 128KB MPC8260 internal memory
; 0xFFE00000 - 0xFFFFFFFF 2MB Flash on CS0
; -----------------------------------------------------------------------------
;
[INIT]
WM32 0x000101A8 0xF0000000 ; IMMR (relocate internal memory)
WREG MSR 0x00000000 ; clear MSR
;WM32 0xF0010000 0x0A200000 ; SIUMCR
WM32 0xF0010004 0xFFFFFFC3 ; SYPCR (no watchdog)
WM32 0xF0010C80 0x00000001 ; SCCR
WM32 0xF0010024 0x80808000 ; BCR
WM8 0xF0010028 0x26 ; PPC_ACR:
WM32 0xF0010040 0x00004000 ; TESCR1:
WM32 0xF0010048 0x00004000 ; L_TESCR1:
;
;
; Memory controller
WM32 0xF0010104 0xFF000C54 ; OR0
WM32 0xF0010100 0xFF001001 ; BR0
;WM32 0xF0010100 0xFFE01001 ; BR0
;WM32 0xF0010104 0xFFE00844 ; OR0
WM32 0xF0010134 0xFE000008 ; OR6 FPGA
WM32 0xF0010130 0x40001001 ; BR6
WM32 0xF001013C 0xFF000C0C ; OR7 RTC
WM32 0xF0010138 0x50001001 ; BR7
WM32 0xF001014C 0xFFFF8008 ; OR9 IDE
WM32 0xF0010148 0x80001001 ; BR9
;
;
; Initialize the SDRAM on the 60x bus.
;
WM32 0xF001010C 0xF8002B00 ; OR1
WM32 0xF0010108 0x00000049 ; BR1
WM32 0xF0010114 0xF8002B00 ; OR2
WM32 0xF0010110 0x08000049 ; BR2
WM16 0xF0010184 0x4000 ; MPTPR
WM8 0xF001019C 0x7 ; PSRT
WM32 0xF0010190 0xAAAE245E ; PSDMR: Precharge all banks
WM8 0x00000000 0xFF ; Access SDRAM
WM32 0xF0010190 0x8AAE245E ; PSDMR: CBR Refresh
WM8 0x00000000 0xFF ; Access SDRAM
WM8 0x00000000 0xFF ; Access SDRAM
WM8 0x00000000 0xFF ; Access SDRAM
WM8 0x00000000 0xFF ; Access SDRAM
WM8 0x00000000 0xFF ; Access SDRAM
WM8 0x00000000 0xFF ; Access SDRAM
WM8 0x00000000 0xFF ; Access SDRAM
WM8 0x00000000 0xFF ; Access SDRAM
WM32 0xF0010190 0x9AAE245E ; PSDMR: Mode Register Write
WM8 0x00000000 0xFF ; Access SDRAM
WM32 0xF0010190 0xC2AE245E ; PSDMR: Normal operation and refresh enable
;
; Initialize the SDRAM on the local bus.
;
WM32 0xF001012C 0xFC002D00 ; OR5
WM32 0xF0010128 0x30001861 ; BR5
WM8 0xF00101A4 0x7 ; LSRT
WM32 0xF0010194 0xAA6A2556 ; LSDMR: Precharge all banks
WM8 0x30000000 0xFF ; Access SDRAM
WM32 0xF0010194 0x8A6A2556 ; LSDMR: CBR Refresh
WM8 0x30000000 0xFF ; Access SDRAM
WM8 0x30000000 0xFF ; Access SDRAM
WM8 0x30000000 0xFF ; Access SDRAM
WM8 0x30000000 0xFF ; Access SDRAM
WM8 0x30000000 0xFF ; Access SDRAM
WM8 0x30000000 0xFF ; Access SDRAM
WM8 0x30000000 0xFF ; Access SDRAM
WM8 0x30000000 0xFF ; Access SDRAM
WM32 0xF0010194 0x9A6A2556 ; LSDMR: Mode Register Write
WM8 0x30000000 0xFF ; Access SDRAM
WM32 0xF0010194 0xC26A2556 ; LSDMR: Normal operation and refresh enable
;
WM16 0x50800206 0x2000 ; Disable flash write protection
;
;
[TARGET]
CPUTYPE 8270 ; 603EV, 750, 8240, 8260, 750CX, or 7400
BDIMODE AGENT ; LOADONLY or AGENT
STARTUP RESET ; RESET, STOP, or RUN
JTAGCLOCK 3 ; 0=16.6MHz, 1=8.3MHz, 2=5.5MHz, 3=4.1MHz
BOOTADDR 0xFFF00100 ; 0xFFF00100 or 0x00000100
WORKSPACE 0x00000000 ; use SDRAM for 256 byte workspace
BREAKMODE HARD ; SOFT or HARD
VECTOR CATCH ; catch unhandled exceptions
DCACHE NOFLUSH ; FLUSH or NOFLUSH
POWERUP 3000
WAKEUP 3000
MMU XLAT 0xC0000000 ; kernel virtual base address
PTBASE 0x000000F0 ; address of page table pointer array
SIO 7 9600
;
;
;
[FLASH]
CHIPTYPE AM29BX16 ; AM29F, AM29BX8, AM29BX16, I28BX8, I28BX16,
; AT49, AT49X8, AT49X16, STRATAX8, STRATAX16
CHIPSIZE 0x200000 ; size of one flash chip in bytes
BUSWIDTH 16 ; flash bus width (8, 16, 32, or 64)
WORKSPACE 0xF0000000 ; use MPC8270 internal RAM for 2KB workspace
ERASE 0xFFE00000 CHIP ; erase entire Flash SIMM
;
;
;
[HOST]
IP 172.30.10.7 ; IP address of tftp server
FILE vmlinuz-est-sbc8260
FORMAT IMAGE 0x0 ; SREC, BIN, AOUT, ELF, IMAGE, or ROM
LOAD MANUAL ; MANUAL or AUTO
DEBUGPORT 2001 ; TCP port number for GDB
PROMPT FW4X60> ; Telnet prompt string
DUMP dump.bin ; default filename for DUMP command
;
;
;
[REGS]
DMM1 0xF0000000
FILE abatron/reg8260.def
[-- Attachment #3: 1432833698-FW8270.CFG --]
[-- Type: application/octet-stream, Size: 6635 bytes --]
; bdiGDB configuration file for MPC8270
; -----------------------------------------------
;
[INIT]
; init core register(MASTER)
WREG MSR 0x00000000 ;clear MSR
;WM32 0xF00101A8 0xF0000000 ;IMMR : internal space @ 0xF0000000
WM32 0xF0010004 0xFFFFFFC3 ;SYPCR: disable watchdog
WM32 0xF0010024 0x80800000 ;BCR:
WM8 0xF0010028 0x26 ;PPC_ACR:
WM32 0xF0010040 0x00004000 ;TESCR1:
WM32 0xF0010048 0x00004000 ;L_TESCR1:
;WM32 0xF0010C80 0x00000001 ;SCCR : normal operation
; init memory controller(master)
WM32 0xF0010104 0xFFE00C54 ;OR0: Flash 2MB, CS early negate, 5 w.s., Timing relax
WM32 0xF0010100 0xFFE01001 ;BR0: Flash @0xFF000000, 16bit, no parity
WM32 0xF001010C 0xF8002B00 ;OR1: 128MBYTE
WM32 0xF0010108 0x00000041 ;BR1: 60x-BUS
WM32 0xF0010114 0xF8002B00 ;OR2: 128MBYTE riki chg fc->f8
WM32 0xF0010110 0x08000041 ;BR2: 60x-BUS
;WM32 0xF001011C 0x00000000 ;OR3: 64MBYTE
;WM32 0xF0010118 0x00000000 ;BR3: 60x-BUS
WM32 0xF001012C 0xFC002F00 ;OR5: 64MBYTE
WM32 0xF0010128 0x30001861 ;BR5: LOCAL-BUS
WM32 0xF0010134 0xFC000008 ;OR6: MAINI-O
WM32 0xF0010130 0x40001001 ;BR6: 60x-BUS
WM32 0xF001013C 0xFF000C0C ;OR7: FPGA-IO
WM32 0xF0010138 0x50001001 ;BR7: 4MBYTE
;WM32 0xF0010144 0xFFFC0100 ;OR8: FUMEI-napa
;WM32 0xF0010140 0x58001081 ;BR8: FUMEI-napa
WM32 0xF001014C 0xFFFF0008 ;OR9: C-FLASH
WM32 0xF0010148 0x80001001 ;BR9: 60x-BUS
; init core register(SLAVE)
;WREG MSR 0x00000000 ;clear MSR
;WM32 0xFF0101A8 0xFF000000 ;IMMR : internal space @ 0xF0000000
WM32 0xFF010004 0xFFFFFFC3 ;SYPCR: disable watchdog
WM32 0xFF010024 0x80800000 ;BCR:
WM8 0xFF010028 0x27 ;PPC_ACR:
WM32 0xFF010040 0x00004000 ;TESCR1:
WM32 0xFF010048 0x00004000 ;L_TESCR1:
;WM32 0xFF010C80 0x00000001 ;SCCR : normal operation
; init SDRAM Init (PPC bus) for CS1&2
WM16 0xF0010184 0xF000 ;MPTPR
WM8 0xF001019C 0xF0 ;PSRT
WM32 0xF0010190 0xAB2DB4AE ;PSDMR: Precharge all banks
WM8 0x00000000 0xFF ;Access SDRAM
WM8 0x08000000 0xFF ;Access SDRAM
WM32 0xF0010190 0x8B2DB4AE ;PSDMR: CBR Refresh
WM8 0x00000000 0xFF ;Access SDRAM
WM8 0x00000000 0xFF ;Access SDRAM
WM8 0x00000000 0xFF ;Access SDRAM
WM8 0x00000000 0xFF ;Access SDRAM
WM8 0x00000000 0xFF ;Access SDRAM
WM8 0x00000000 0xFF ;Access SDRAM
WM8 0x00000000 0xFF ;Access SDRAM
WM8 0x00000000 0xFF ;Access SDRAM
WM8 0x08000000 0xFF ;Access SDRAM
WM8 0x08000000 0xFF ;Access SDRAM
WM8 0x08000000 0xFF ;Access SDRAM
WM8 0x08000000 0xFF ;Access SDRAM
WM8 0x08000000 0xFF ;Access SDRAM
WM8 0x08000000 0xFF ;Access SDRAM
WM8 0x08000000 0xFF ;Access SDRAM
WM8 0x08000000 0xFF ;Access SDRAM
WM32 0xF0010190 0x9B2DB4AE ;PSDMR: Mode Set
WM8 0x00088110 0xFF ;Access SDRAM
WM8 0x08088110 0xFF ;Access SDRAM
WM32 0xF0010190 0xc32DB4AE ;PSDMR: enable refresh, normal operation
WM16 0x50800206 0x2000 ;flash-protect-disable
; init SDRAM Init (LOCAL bus) for CS5
WM8 0xF00101A4 0xF0 ;LSRT
WM32 0xF0010194 0xAB41B4AE ;LSDMR: Precharge all banks
WM8 0x30000000 0xFF ;Access SDRAM
WM32 0xF0010194 0x8B41B4AE ;LSDMR: CBR Refresh
WM8 0x30000000 0xFF ;Access SDRAM
WM8 0x30000000 0xFF ;Access SDRAM
WM8 0x30000000 0xFF ;Access SDRAM
WM8 0x30000000 0xFF ;Access SDRAM
WM8 0x30000000 0xFF ;Access SDRAM
WM8 0x30000000 0xFF ;Access SDRAM
WM8 0x30000000 0xFF ;Access SDRAM
WM8 0x30000000 0xFF ;Access SDRAM
WM32 0xF0010194 0x9B41B4AE ;LSDMR: Mode Set
WM8 0x30044088 0xFF ;Access SDRAM
WM32 0xF0010194 0xC341B4AE ;LSDMR: enable refresh, normal operation
; init memory controller(slave)
;WM32 0xFF010104 0xFFE00C54 ;OR0: Flash 2MB, CS early negate, 5 w.s., Timing relax
WM32 0xFF010100 0x00000000 ;BR0: Flash @0xFF000000, 16bit, no parity
;WM32 0xFF01010C 0xF8002B00 ;OR1: 128MBYTE
;WM32 0xFF010108 0x00000041 ;BR1: 60x-BUS
;WM32 0xFF010114 0xF8002B00 ;OR2: 128MBYTE riki chg fc->f8
;WM32 0xFF010110 0x08000041 ;BR2: 60x-BUS
;WM32 0xFF01011C 0x00000000 ;OR3: 64MBYTE
;WM32 0xFF010118 0x00000000 ;BR3: 60x-BUS
;WM32 0xFF01012C 0xFC002F00 ;OR5: 64MBYTE
;WM32 0xFF010128 0x30001861 ;BR5: LOCAL-BUS
;WM32 0xFF010134 0xFC000008 ;OR6: MAINI-O
;WM32 0xFF010130 0x40001001 ;BR6: 60x-BUS
;WM32 0xFF01013C 0xFF000C0C ;OR7: FPGA-IO
;WM32 0xFF010138 0x50001001 ;BR7: 4MBYTE
;WM32 0xFF010144 0xFFFC0100 ;OR8: FUMEI-napa
;WM32 0xFF010140 0x58001081 ;BR8: FUMEI-napa
;WM32 0xFF01014C 0xFFFF0008 ;OR9: C-FLASH
;WM32 0xFF010148 0x80001001 ;BR9: 60x-BUS
[TARGET]
CPUTYPE 8270 ;the CPU type (603EV,750,8240,8260)
JTAGCLOCK 0 ;use 16 MHz JTAG clock
BOOTADDR 0xfff00100 ;boot address used for start-up break
WORKSPACE 0x0e000000 ;workspace in target RAM for fast download
BDIMODE AGENT ;the BDI working mode (LOADONLY | AGENT | GATEWAY)
BREAKMODE SOFT ;SOFT or HARD, HARD uses PPC hardware breakpoints
;STEPMODE HWBP ;TRACE or HWBP, HWPB uses a hardware breakpoint
VECTOR CATCH ;catch unhandled exceptions
DCACHE NOFLUSH ;data cache flushing (FLUSH | NOFLUSH)
;MMU XLAT ;translate effective to physical address
POWERUP 1000 ;start delay after power-up detected in ms
;REGLIST SPR ;select register to transfer to GDB
;REGLIST ALL ;select register to transfer to GDB
;VIO 7 9600 ;TCP port for virtual IO, BCSR1: enable RS232-1 !!!
;SIO 7 9600 ;TCP port for serial IO, check BCSR1: enable RS232-1 !!!
[HOST]
IP 192.168.0.3
FILE D:\cygwin\home\riki\ram-test-data\make_bin_inc_256M.bin
FORMAT BIN 0x00000000
LOAD MANUAL ;load code MANUAL or AUTO after reset
DEBUGPORT 2001
PROMPT MPC8270> ;new prompt for Telnet
DUMP D:\cygwin\home\riki\temp\dump.bin
[FLASH]
CHIPTYPE AM29BX16 ;Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | I28BX16)
;CHIPTYPE AM29BX8
CHIPSIZE 0x200000 ;The size of one flash chip in bytes (e.g. AM29F010 = 0x20000)
BUSWIDTH 16 ;The width of the flash memory bus in bits (8 | 16 | 32 | 64)
;WORKSPACE 0x04700000 ;workspace in dual port RAM
WORKSPACE 0x00000000 ;workspace in SDRAM
;FILE E:\tornado\target\config\ads8260\test.hex ;The file to program
FORMAT BIN
FILE D:\tftpboot\u-boot.bin
;
ERASE 0xFFE00000 CHIP ;ERASE WHOLE CHIP
[REGS]
DMM1 0xF0000000
FILE C:\BDI\CONFIG\reg8270.def
reply other threads:[~2006-06-14 16:40 UTC|newest]
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