From: Olof Johansson <olof@lixom.net>
To: paulus@samba.org, anton@samba.org
Cc: linuxppc-dev@ozlabs.org
Subject: [patch 0/5] [v2] powerpc: PA Semi PWRficient patches
Date: Tue, 5 Sep 2006 18:43:16 -0500 [thread overview]
Message-ID: <20060905184316.4c1a460b@localhost.localdomain> (raw)
Hi,
The following series of patches introduces basic support for PA Semi's
PA6T core, and the base platform support for PWRficient PA6T-1682M.
It is split up in 5 separate patches:
1. Reduce default cacheline size to 64 bytes
2. Divorce CPU_FTR_CTRL from CPU_FTR_PPCAS_ARCH_V2_BASE
3. Cpu table entry, PVR value
4. Basic arch/powerpc/platforms/pasemi contents
5. MAINTAINER entry
Changes since last submission:
* Include file cleanup (Roland)
* Whitespace/line length fixes (Mikey, Joel)
* Kill linux,pci-domain stuff (Ben)
* Remove loops_per_jiffy default (Ben)
* Enforce PCI-e config space addressing (Ben)
* Whitespace, init, cast fixes (Arnd)
* Prototypes -> pasemi.h (Arnd)
* Kill some of the RTC stubs (Arnd)
-Olof
next reply other threads:[~2006-09-05 23:48 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-09-05 23:43 Olof Johansson [this message]
2006-09-05 23:47 ` [patch 1/5] [v2] powerpc: Reduce default cacheline size to 64 bytes Olof Johansson
2006-09-05 23:47 ` [patch 2/5] [v2] powerpc: Divorce CPU_FTR_CTRL from CPU_FTR_PPCAS_ARCH_V2_BASE Olof Johansson
2006-09-05 23:47 ` [patch 3/5] [v2] powerpc: PA6T cputable entry, PVR value Olof Johansson
2006-09-05 23:47 ` [patch 4/5] [v2] powerpc: PA Semi PWRficient platform support Olof Johansson
2006-09-05 23:47 ` [patch 5/5] [v2] powerpc: PA Semi PWRficient MAINTAINER entry Olof Johansson
2006-09-06 0:17 ` [patch 0/5] [v2] powerpc: PA Semi PWRficient patches Michael Ellerman
2006-09-06 1:41 ` Olof Johansson
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