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From: Olof Johansson <olof@lixom.net>
To: paulus@samba.org, anton@samba.org
Cc: linuxppc-dev@ozlabs.org
Subject: [patch 0/5] [v3] powerpc: PA Semi PWRficient patches
Date: Wed, 6 Sep 2006 14:33:05 -0500	[thread overview]
Message-ID: <20060906143305.05b54abb@localhost.localdomain> (raw)

Hi,

The following series of patches introduces basic support for PA Semi's
PA6T core, and the base platform support for PWRficient PA6T-1682M.

It is split up in 5 separate patches:

1. Reduce default cacheline size to 64 bytes
2. Divorce CPU_FTR_CTRL from CPU_FTR_PPCAS_ARCH_V2_BASE
3. Cpu table entry, PVR value
4. Basic arch/powerpc/platforms/pasemi contents
5. MAINTAINER entry


Changes since last submission:

* Fix host bridge ioremap typo (Segher)
* Misc IRQ cleanup (Segher)


-Olof

             reply	other threads:[~2006-09-06 19:46 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2006-09-06 19:33 Olof Johansson [this message]
2006-09-06 19:34 ` [patch 1/5] [v3] powerpc: Reduce default cacheline size to 64 bytes Olof Johansson
2006-09-06 19:35 ` [patch 2/5] [v3] powerpc: Divorce CPU_FTR_CTRL from CPU_FTR_PPCAS_ARCH_V2_BASE Olof Johansson
2006-09-06 19:35 ` [patch 3/5] [v3] powerpc: PA6T cputable entry, PVR value Olof Johansson
2006-09-06 19:42 ` [patch 4/5] [v3] powerpc: PA Semi PWRficient platform support Olof Johansson
2006-09-06 19:44 ` [patch 5/5] [v3] powerpc: PA Semi PWRficient MAINTAINER entry Olof Johansson

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