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From: Olof Johansson <olof@lixom.net>
To: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: linuxppc-dev@ozlabs.org, Paul Mackerras <paulus@samba.org>
Subject: Re: [PATCH] Lazy interrupt disabling for 64-bit machines
Date: Tue, 26 Sep 2006 10:43:13 -0500	[thread overview]
Message-ID: <20060926104313.06653807@pb15> (raw)
In-Reply-To: <1159261926.5462.54.camel@localhost.localdomain>

On Tue, 26 Sep 2006 19:12:06 +1000 Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote:

> 
> > I like it. Got any benchmarks that show a difference?
> > 
> > At first glance I found it a bit hard to follow, since the old+new
> > terminology is a bit complicated. There's softe, proc_enabled and
> > hard_enabled. A s/proc_enabled/soft_enabled/g (and similar for
> > asm-offsets) might make it a little more intuitive, since you're
> > touching most uses of it already?
> 
> Now think about using -ffixed=crN ... reserve a CR field and use that
> for per-cpu flags like that :)

You can also get away from doing the mfspr(SPRN_DEC) in
local_irq_enable() by changing the polarity of hard_enabled to
hard_disabled, and have different values for why it was disabled. Saves
an mfspr which can be costly, but adds one instruction (li (n>>8) or
so) in the exception entry path. Not which way that tradeoff will
swing, without benchmarking to show benefit it's just added complexity.

That can be done with a fixed cr too, it just uses two bits instead of
one. There are fewer to take from there though.


-Olof

  parent reply	other threads:[~2006-09-26 15:43 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2006-09-26  4:55 [PATCH] Lazy interrupt disabling for 64-bit machines Paul Mackerras
2006-09-26  5:30 ` Michael Ellerman
2006-09-26  6:10 ` Olof Johansson
2006-09-26  9:12   ` Benjamin Herrenschmidt
2006-09-26 10:31     ` Gabriel Paubert
2006-09-26 15:43     ` Olof Johansson [this message]
  -- strict thread matches above, loose matches on Subject: below --
2006-10-04  6:47 Paul Mackerras

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