From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from web8414.mail.in.yahoo.com (web8414.mail.in.yahoo.com [202.43.219.102]) by ozlabs.org (Postfix) with SMTP id CD77DDDF61 for ; Wed, 17 Jan 2007 10:27:16 +1100 (EST) Message-ID: <20070116232034.40662.qmail@web8414.mail.in.yahoo.com> Date: Tue, 16 Jan 2007 23:20:34 +0000 (GMT) From: agnel juni Subject: PCI IRQ -MPC8540 To: Kumar Gala MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="0-737655938-1168989634=:37604" Cc: linuxppc-embedded@ozlabs.org List-Id: Linux on Embedded PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , --0-737655938-1168989634=:37604 Content-Type: text/plain; charset=ascii Content-Transfer-Encoding: quoted-printable Hello all:=0A=0AI would like to understand if there is a way to program the= PCI interrupt pin register of MPC8540. I did look for this in the datashee= t, but couldn't find any positive answer.=0A=0ACurrently, I am working in a= set-up where MPC8540 is an agent, plugged into the PC host. =0AI couldn't = get an IRQ for the card when plugged in some PCI slots, whereas in one of t= he slots I do see a non-zero value.=0A=0AIt would be great if you could hel= p me understand the issue.=0A=0AI am sorry if the question is inapporpriate= in the group. I am desperate to solve the issue.=0A=0AThanks for any help.= =0AJ.Joseph=0A=0A----- Original Message ----=0AFrom: Kumar Gala =0ATo: Wang Matthew-R59995 =0ACc: linux= ppc-embedded@ozlabs.org=0ASent: Wednesday, 18 October, 2006 6:54:24 PM=0ASu= bject: Re: Linuxppc-embedded Digest, Vol 26, Issue 36=0A=0A=0AOn Oct 18, 20= 06, at 8:10 PM, Wang Matthew-R59995 wrote:=0A=0A> Hi Kumar,=0A>=0A> Actuall= y I do many trials about it. Vxwerks Bootrom is smaller than=0A> U-Boot. Th= e key difference between Bootrom and U-boot is that some=0A> source code of= Bootrom is invisible to the users.=0A>=0A> Actually the rfi instruction wh= ich I point out is the first rfi=0A> instruction of Linux PowerPC bringup.= =0A>=0A> Before that, it's TLB entry invalidation and temp TLB entry mappin= g.=0A>=0A> I check MMU setting carefully before coming Linux Kernel.=0A>=0A= > I just want to know if other guys met similar scenario like me. I =0A> d= on't=0A> need the precise answer, just overall suggestion about it because = I=0A> understand that not everyone has the same bootloader of mine, that=0A= > bootloader is actually a customized bootloader.=0A=0AI understand that, t= hus I was asking what exact problem you were =0Aseeing to try and help.=0A= =0A> Anyway thank you.=0A>=0A> R9 point to LR register, mask the high 20 bi= t of r9 and send to r7, =0A> and=0A> then add 24, which means stride 6 ins= tructions for rfi instruction=0A> execution.=0A>=0A> Of course, rfi can swi= tch the TLB entry, both the previous TLB =0A> entry and=0A> the temp TLB e= ntry point to the same physical address.=0A>=0A> I've checked it.=0A=0AI kn= ow what the code does, I wrote it :)=0A=0A- kumar=0A=0A=0A=0A______________= _________________________________=0ALinuxppc-embedded mailing list=0ALinuxp= pc-embedded@ozlabs.org=0Ahttps://ozlabs.org/mailman/listinfo/linuxppc-embed= ded=0A=0A=0A=0A=0A=0A=0A=0A=09=09=0A_______________________________________= ___________________=0AYahoo! India Answers: Share what you know. Learn some= thing new=0Ahttp://in.answers.yahoo.com/ --0-737655938-1168989634=:37604 Content-Type: text/html; charset=iso-8859-7 Content-Transfer-Encoding: quoted-printable
Hello all:

I would like to understand if the= re is a way to program the PCI interrupt pin register of MPC8540. I did loo= k for this in the datasheet, but couldn't find any positive answer.

= Currently, I am working in a set-up where MPC8540 is an agent, plugged into= the PC host.
I couldn't get an IRQ for the card when plugged in some P= CI slots, whereas in one of the slots I do see a non-zero value.

It = would be great if you could help me understand the issue.

I am sorry= if the question is inapporpriate in the group. I am desperate to solve the= issue.

Thanks for any help.
J.Joseph

----- Origin= al Message ----
From: Kumar Gala <galak@kernel.crashing.org>
To: Wang Mat= thew-R59995 <Qi.W@freescale.com>
Cc: linuxppc-embedded@ozlabs.org<= br>Sent: Wednesday, 18 October, 2006 6:54:24 PM
Subject: Re: Linuxppc-em= bedded Digest, Vol 26, Issue 36


On Oct 18, 2006, at 8:10 PM= , Wang Matthew-R59995 wrote:

> Hi Kumar,
>
> Actually= I do many trials about it. Vxwerks Bootrom is smaller than
> U-Boot.= The key difference between Bootrom and U-boot is that some
> source = code of Bootrom is invisible to the users.
>
> Actually the rfi= instruction which I point out is the first rfi
> instruction of Linu= x PowerPC bringup.
>
> Before that, it's TLB entry invalidation= and temp TLB entry mapping.
>
> I check MMU setting carefully = before coming Linux Kernel.
>
> I just want to know if other gu= ys met similar scenario like me. I  
> don't
> need t= he precise answer, just overall suggestion about it because I
> understand that= not everyone has the same bootloader of mine, that
> bootloader is a= ctually a customized bootloader.

I understand that, thus I was askin= g what exact problem you were  
seeing to try and help.
> Anyway thank you.
>
> R9 point to LR register, mask the h= igh 20 bit of r9 and send to r7,  
> and
> then add 2= 4, which means stride 6 instructions for rfi instruction
> execution.=
>
> Of course, rfi can switch the TLB entry, both the previous= TLB  
> entry and
> the temp TLB entry point to the = same physical address.
>
> I've checked it.

I know what = the code does, I wrote it :)

- kumar



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