Hi,

I am using to the LSI SAS MEGARAID SAS 8480E adapter. And I am under debugging u-boot-1.2.0. u-boot-1.2.0 and kernel-2.6.20(denx's git) don't include the code to scan and setup under pcie bridge, Right?

I have checked the LSI adapter at general linux system. The structure of the LSI Adapter is the following. I don’t know exactly why only bridge find and setup at u-boot. Help me please.

=====================================================================================

[root@node-5 ~]# lspci

06:08.0 SCSI storage controller: LSI Logic / Symbios Logic: Unknown device 0054 (rev 01)

Subsystem: LSI Logic / Symbios Logic: Unknown device 1000

Flags: bus master, 66Mhz, medium devsel, latency 64, IRQ 11

I/O ports at d000 [size=256]

Memory at dfffc000 (64-bit, non-prefetchable) [size=16K]

Memory at dffe0000 (64-bit, non-prefetchable) [size=64K]

Expansion ROM at dfc00000 [disabled] [size=2M]

Capabilities: [50] Power Management version 2

Capabilities: [98] Message Signalled Interrupts: 64bit+ Queue=0/0 Enable-

Capabilities: [68] PCI-X non-bridge device.

06:0e.0 Memory controller: Intel Corp.: Unknown device 0374

Flags: bus master, stepping, 66Mhz, medium devsel, latency 64, IRQ 6

Memory at e7000000 (64-bit, prefetchable) [size=16M]

Capabilities: [c0] Power Management version 2

Capabilities: [d0] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable-

Capabilities: [e0] PCI-X non-bridge device.

[root@node-5 ~]# lspci -t

-[0000:00]-+-00.0

+-01.0-[0000:07]----00.0

+-1b.0

+-1c.0-[0000:04-06]--+-00.0-[0000:06]--+-08.0

| | \-0e.0

| \-00.2-[0000:05]--

+-1c.4-[0000:03]----00.0

+-1c.5-[0000:02]----00.0

+-1d.0

+-1d.1

+-1d.2

+-1d.3

+-1d.7

+-1e.0-[0000:01]--+-03.0

| \-04.0

+-1f.0

+-1f.1

+-1f.2

\-1f.3

=====================================================================================

The following text is printing at u-boot

U-Boot 1.2.0 (Feb 24 2007 - 12:11:00)

CPU: AMCC PowerPC 440SPe Rev. B at 533.328 MHz (PLB=133, OPB=66, EBC=66 MHz)

RAID 6 support

I2C boot EEPROM enabled

Bootstrap Option D - Boot ROM Location I2C (Addr 0x50)

Internal PCI arbiter enabled

32 kB I-Cache 32 kB D-Cache

Board: Yucca - AMCC 440SPe Evaluation Board

I2C: ready

DRAM: DIMM slot 0: DDR2 SDRAM detected

DIMM slot 1: DDR2 SDRAM detected

1024 MB

Now running in RAM - U-Boot at: 3ffb2000

FLASH: 5 MB

*** Warning - bad CRC, using default environment

PCI: Bus Dev VenId DevId Class Int

PCI Autoconfig: Memory region: [80000000-8fffffff]

PCI Autoconfig: I/O region: [0-ffff]

PCIE:1 successfully set as rootpoint

PCI Autoconfig: Memory region: [b1000000-b1ffffff]

PCI Scan: Found Bus 1, Device 1, Function 0