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From: Gabriel Paubert <paubert@iram.es>
Date: Thu, 12 Apr 2007 10:31:36 +0200
To: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Subject: Re: [patch 3/3] cell: prevent alignment interrupt on local store
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Cc: Olaf Hering <olaf@aepfle.de>, Arnd Bergmann <arnd@arndb.de>,
	Akinobu Mita <mita@fixstars.com>, linuxppc-dev@ozlabs.org,
	Paul Mackerras <paulus@samba.org>, cbe-oss-dev@ozlabs.org
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On Thu, Apr 12, 2007 at 04:38:10PM +1000, Benjamin Herrenschmidt wrote:
> On Thu, 2007-04-12 at 08:33 +0200, Olaf Hering wrote:
> > On Thu, Apr 12, Benjamin Herrenschmidt wrote:
> > 
> > > Gets altivec and stops working on POWER5 ? no deal :-)
> > 
> > If there is a significant performance gain (not only 9%) and if
> > -mcpu=$cell does not generate instructions that wont work on other
> > altivec capable cpus and if rpm gets a target ppcaltivec.rpm (or
> > similar), as separate binary tree can be done.
> 
> -mcpu=cell can possibly generate things that won't run on 970 and 74xx.
> There are some new altivec instructions among others...

Any pointer to a document describing the differences?

	Regards,
	Gabriel