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From: "Rick Moleres" <Rick.Moleres@xilinx.com>
To: "Joachim Förster" <mls.JOFT@gmx.de>, linuxppc-embedded@ozlabs.org
Subject: RE: ML403 and PPC4xx_DMA ?
Date: Thu, 26 Apr 2007 15:36:56 -0600	[thread overview]
Message-ID: <20070426213657.CAFF7630046@mail101-cpk.bigfish.com> (raw)
In-Reply-To: <1177603586.5532.20.camel@localhost>


Joachim,

The Xilinx PPC405 core does not have an integrated DMA controller.

-----Original Message-----
From: linuxppc-embedded-bounces+moleres=3Dxilinx.com@ozlabs.org =
[mailto:linuxppc-embedded-bounces+moleres=3Dxilinx.com@ozlabs.org] On =
Behalf Of Joachim F=F6rster
Sent: Thursday, April 26, 2007 10:06 AM
To: linuxppc-embedded@ozlabs.org
Subject: ML403 and PPC4xx_DMA ?

Hi all,

I have a question regarding the PowerPC 405 Core on the Xilinx ML403
board and DMA . The Linux kernel has an option called CONFIG_PPC4xx_DMA.
Do all/some PowerPC 4xx Cores have an integrated DMA Controller? I tried
to find some documentation about this DMA Controller in several Xilinx
and IBM manuals which cover the PowerPC 405 Core - but I didn't find
anything.
So, my question is: Does the Virtex-4 FX12 PowerPC 405 Core on the ML403
have such DMA Controller? If yes, is it usable within Linux to transfer
data from RAM to a device's hardware buffers (typical task of a DMA
controller)?

Thanks,
 Joachim

PS: I tried to compile a kernel image with CONFIG_PPC4xx_DMA enabled,
but gcc complains about missing definitions in ppc4xx_dma.c ... e.g.
DCRN_DMASR (defined in ibm405.h). Well I guess I have to have
DCRN_MASR_BASE defined in xparameters_ml403.h .... but defined to what?


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      parent reply	other threads:[~2007-04-26 21:37 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2007-04-26 16:06 ML403 and PPC4xx_DMA ? Joachim Förster
2007-04-26 19:51 ` rvk
2007-04-26 21:36 ` Rick Moleres [this message]

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