Re: [RFC] SystemACE driver - abstract register ops

[Wolfgang Reissnegger <wolfgang.reissnegger@xilinx.com>]

Hi Peter,

thanks for the feedback.

Yes, I agree. Having the code in mainline would be most preferable. 
However, there is always a delay between when people submit patches and 
when code actually does get into mainline. Also, it's not always 
guaranteed that the code is actually accepted into mainline. In the 
meantime there are a multitude of patches floating around which IMHO can 
be quite confusing.

The purpose of the "Xilinx git tree" is to provide a central place where 
those patches can be accumulated, including PPC and MicroBlaze. Also, as 
Xilinx is creating new IP cores, drivers for those cores will be 
directly added to that tree, eliminating the EDK->Linux horrors.

So, yes, I think it's partly a staging area for code that should make it 
into mainline, but it's also a repository for code that is not accepted 
into mainline (yet), or new, or otherwise useful to the community.

Wolfgang

Peter Korsgaard wrote:
>>>>>> "WR" == Wolfgang Reissnegger <wolfgang.reissnegger@xilinx.com> writes:
> 
> Hi,
> 
> WR> The end goal is to have a kernel tree that contains ALL Xilinx
> WR> drivers and the multitude of drivers that are being
> WR> created/updated and contributed here. Having such a kernel
> WR> available will simplify the process of bringing up a new
> WR> system. The hope is that contributors will adopt the idea of
> WR> having a "Xilinx" kernel and will start using that tree as a "base
> WR> reference".
> 
> But there already is such a tree - It's called 'mainline'. I can see
> some advantage in having a Xilinx tree as a staging area, but it
> really HAS to be a temporary thing and stuff needs to be pushed to
> mainline.
> 
> WR> I will post news here as they unfold. In the meantime it would be
> WR> very interesting to hear ideas and suggestions from you. Concerns
> WR> that people have. Pitfalls to look out for etc.
> 
> Hereby my 2 cents.
>