MPC85xx_MDS: Patches to support QE, UCCs and SPI

MPC85xx_MDS: Patches to support QE, UCCs and SPI

[Anton Vorontsov]

Hi all,

These patches needed to make QE, UCCs and SPI work on MPC8568E-MDS.

Patchset is against galak/powerpc.git master branch.

Thanks,

-- 
Anton Vorontsov
email: cbou@mail.ru
backup email: ya-cbou@yandex.ru
irc://irc.freenode.net/bd2

[PATCH 1/7] [POWERPC] mpc85xx_mds: select QUICC_ENGINE

[Anton Vorontsov]

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
 arch/powerpc/platforms/85xx/Kconfig |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index b8476b2..cf815b2 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -25,7 +25,7 @@ config MPC85xx_CDS
 config MPC85xx_MDS
 	bool "Freescale MPC85xx MDS"
 	select DEFAULT_UIMAGE
-#	select QUICC_ENGINE
+	select QUICC_ENGINE
 	help
 	  This option enables support for the MPC85xx MDS board
 
-- 
1.5.0.6

[PATCH 2/7] [POWERPC] Fix QEIC->MPIC cascading

[Anton Vorontsov]

set_irq_chained_handler overwrites MPIC's handle_irq function
(handle_fasteoi_irq) thus MPIC never gets eoi event from the
cascaded IRQ. This situation hangs MPIC on MPC8568E.

Patch adds flow level "end" handler to the MPIC, and QEIC calls
it when QEIC's interrupt processing finished.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
 arch/powerpc/sysdev/mpic.c         |    3 +++
 arch/powerpc/sysdev/qe_lib/qe_ic.c |    6 ++++++
 2 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 8de29f2..bee2d5b 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -846,6 +846,7 @@ static struct irq_chip mpic_irq_chip = {
 	.mask		= mpic_mask_irq,
 	.unmask		= mpic_unmask_irq,
 	.eoi		= mpic_end_irq,
+	.end		= mpic_end_irq,
 	.set_type	= mpic_set_irq_type,
 };
 
@@ -854,6 +855,7 @@ static struct irq_chip mpic_ipi_chip = {
 	.mask		= mpic_mask_ipi,
 	.unmask		= mpic_unmask_ipi,
 	.eoi		= mpic_end_ipi,
+	.end		= mpic_end_ipi,
 };
 #endif /* CONFIG_SMP */
 
@@ -864,6 +866,7 @@ static struct irq_chip mpic_irq_ht_chip = {
 	.mask		= mpic_mask_irq,
 	.unmask		= mpic_unmask_ht_irq,
 	.eoi		= mpic_end_ht_irq,
+	.end		= mpic_end_ht_irq,
 	.set_type	= mpic_set_irq_type,
 };
 #endif /* CONFIG_MPIC_U3_HT_IRQS */
diff --git a/arch/powerpc/sysdev/qe_lib/qe_ic.c b/arch/powerpc/sysdev/qe_lib/qe_ic.c
index 55e6f39..8e743e0 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_ic.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_ic.c
@@ -328,6 +328,9 @@ void qe_ic_cascade_low(unsigned int irq, struct irq_desc *desc)
 
 	if (cascade_irq != NO_IRQ)
 		generic_handle_irq(cascade_irq);
+
+	if (desc->chip->end)
+		desc->chip->end(irq);
 }
 
 void qe_ic_cascade_high(unsigned int irq, struct irq_desc *desc)
@@ -337,6 +340,9 @@ void qe_ic_cascade_high(unsigned int irq, struct irq_desc *desc)
 
 	if (cascade_irq != NO_IRQ)
 		generic_handle_irq(cascade_irq);
+
+	if (desc->chip->end)
+		desc->chip->end(irq);
 }
 
 void __init qe_ic_init(struct device_node *node, unsigned int flags)
-- 
1.5.0.6

[PATCH 3/7] [POWERPC] QEIC: implement low+high multiplexed IRQ chained handler

[Anton Vorontsov]

For MPC8568E low and high QEIC lines routed to the single MPIC
input, thus low and high sources should be demultiplexed.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
 arch/powerpc/sysdev/qe_lib/qe_ic.c |   34 ++++++++++++++++++++++++++++------
 1 files changed, 28 insertions(+), 6 deletions(-)

diff --git a/arch/powerpc/sysdev/qe_lib/qe_ic.c b/arch/powerpc/sysdev/qe_lib/qe_ic.c
index 8e743e0..0ecb614 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_ic.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_ic.c
@@ -345,6 +345,22 @@ void qe_ic_cascade_high(unsigned int irq, struct irq_desc *desc)
 		desc->chip->end(irq);
 }
 
+static void qe_ic_cascade_muxed(unsigned int irq, struct irq_desc *desc)
+{
+	struct qe_ic *qe_ic = desc->handler_data;
+	unsigned int cascade_irq;
+
+	cascade_irq = qe_ic_get_high_irq(qe_ic);
+	if (cascade_irq == NO_IRQ)
+		cascade_irq = qe_ic_get_low_irq(qe_ic);
+
+	if (cascade_irq != NO_IRQ)
+		generic_handle_irq(cascade_irq);
+
+	if (desc->chip->end)
+		desc->chip->end(irq);
+}
+
 void __init qe_ic_init(struct device_node *node, unsigned int flags)
 {
 	struct qe_ic *qe_ic;
@@ -404,12 +420,18 @@ void __init qe_ic_init(struct device_node *node, unsigned int flags)
 
 	qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
 
-	set_irq_data(qe_ic->virq_low, qe_ic);
-	set_irq_chained_handler(qe_ic->virq_low, qe_ic_cascade_low);
-
-	if (qe_ic->virq_high != NO_IRQ) {
-		set_irq_data(qe_ic->virq_high, qe_ic);
-		set_irq_chained_handler(qe_ic->virq_high, qe_ic_cascade_high);
+	if (qe_ic->virq_high == qe_ic->virq_low) {
+		set_irq_data(qe_ic->virq_low, qe_ic);
+		set_irq_chained_handler(qe_ic->virq_low, qe_ic_cascade_muxed);
+	} else {
+		set_irq_data(qe_ic->virq_low, qe_ic);
+		set_irq_chained_handler(qe_ic->virq_low, qe_ic_cascade_low);
+
+		if (qe_ic->virq_high != NO_IRQ) {
+			set_irq_data(qe_ic->virq_high, qe_ic);
+			set_irq_chained_handler(qe_ic->virq_high,
+						qe_ic_cascade_high);
+		}
 	}
 
 	printk("QEIC (%d IRQ sources) at %p\n", NR_QE_IC_INTS, qe_ic->regs);
-- 
1.5.0.6

[PATCH 4/7] [POWERPC] QE pario: support for MPC85xx layout

[Anton Vorontsov]

8 bytes padding required to match MPC85xx registers layout.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
 arch/powerpc/sysdev/qe_lib/qe_io.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/sysdev/qe_lib/qe_io.c b/arch/powerpc/sysdev/qe_lib/qe_io.c
index e32b45b..d566e89 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_io.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_io.c
@@ -36,6 +36,9 @@ struct port_regs {
 	__be32	cpdir2;		/* Direction register */
 	__be32	cppar1;		/* Pin assignment register */
 	__be32	cppar2;		/* Pin assignment register */
+#ifdef CONFIG_MPC85xx
+	u8	pad[8];
+#endif
 };
 
 static struct port_regs *par_io = NULL;
-- 
1.5.0.6

[PATCH 5/7] [POWERPC] mpc8568mds: update dts to be able to use UCCs

[Anton Vorontsov]

1. UCC1's RX_DV pin is 16, not 15;
2. UCC1's phy is at 0x7, not 0x1. Schematics says 0x7, and recent
   u-boot also using 0x7.
3. Use gianfar's (eTSEC) mdio bus. This is hardware default setup.
4. tx-clock should be CLK16 (GE125, PB31);
5. phy-connection-type is RGMII-ID;

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
 arch/powerpc/boot/dts/mpc8568mds.dts |   22 +++++++++++-----------
 1 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index c472a4b..1d082fb 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -95,10 +95,10 @@
 			device_type = "mdio";
 			compatible = "gianfar";
 			reg = <24520 20>;
-			phy0: ethernet-phy@0 {
+			phy0: ethernet-phy@7 {
 				interrupt-parent = <&mpic>;
 				interrupts = <1 1>;
-				reg = <0>;
+				reg = <7>;
 				device_type = "ethernet-phy";
 			};
 			phy1: ethernet-phy@1 {
@@ -286,7 +286,7 @@
 					4  1a  2  0  2  0 	/* RxD7 */
 					4  0b  1  0  2  0 	/* TX_EN */
 					4  18  1  0  2  0 	/* TX_ER */
-					4  0f  2  0  2  0 	/* RX_DV */
+					4  10  2  0  2  0 	/* RX_DV */
 					4  1e  2  0  2  0 	/* RX_ER */
 					4  11  2  0  2  0 	/* RX_CLK */
 					4  13  1  0  2  0 	/* GTX_CLK */
@@ -377,10 +377,10 @@
 			mac-address = [ 00 00 00 00 00 00 ];
 			local-mac-address = [ 00 00 00 00 00 00 ];
 			rx-clock = <0>;
-			tx-clock = <19>;
-			phy-handle = <&qe_phy0>;
-			phy-connection-type = "gmii";
+			tx-clock = <20>;
 			pio-handle = <&pio1>;
+			phy-handle = <&phy0>;
+			phy-connection-type = "rgmii-id";
 		};
 
 		ucc@3000 {
@@ -399,10 +399,10 @@
 			mac-address = [ 00 00 00 00 00 00 ];
 			local-mac-address = [ 00 00 00 00 00 00 ];
 			rx-clock = <0>;
-			tx-clock = <14>;
-			phy-handle = <&qe_phy1>;
-			phy-connection-type = "gmii";
+			tx-clock = <20>;
 			pio-handle = <&pio2>;
+			phy-handle = <&phy1>;
+			phy-connection-type = "rgmii-id";
 		};
 
 		mdio@2120 {
@@ -414,10 +414,10 @@
 
 			/* These are the same PHYs as on
 			 * gianfar's MDIO bus */
-			qe_phy0: ethernet-phy@00 {
+			qe_phy0: ethernet-phy@07 {
 				interrupt-parent = <&mpic>;
 				interrupts = <1 1>;
-				reg = <0>;
+				reg = <7>;
 				device_type = "ethernet-phy";
 			};
 			qe_phy1: ethernet-phy@01 {
-- 
1.5.0.6

[PATCH 6/7] [POWERPC] mpc85xx_mds: reset UCC ethernet properly

[Anton Vorontsov]

Apart from that the current code doesn't compile it's also
meaningless with regard to the MPC8568E-MDS' BCSR.

This patch used to reset UCCs properly.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
 arch/powerpc/platforms/85xx/mpc85xx_mds.c |   28 ++++++++++++++++------------
 1 files changed, 16 insertions(+), 12 deletions(-)

diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index c379286..5de409b 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -107,18 +107,22 @@ static void __init mpc85xx_mds_setup_arch(void)
 	}
 
 	if (bcsr_regs) {
-		u8 bcsr_phy;
-
-		/* Reset the Ethernet PHY */
-		bcsr_phy = in_be8(&bcsr_regs[9]);
-		bcsr_phy &= ~0x20;
-		out_be8(&bcsr_regs[9], bcsr_phy);
-
-		udelay(1000);
-
-		bcsr_phy = in_be8(&bcsr_regs[9]);
-		bcsr_phy |= 0x20;
-		out_be8(&bcsr_regs[9], bcsr_phy);
+#define BCSR_UCC1_GETH_EN	(0x1 << 7)
+#define BCSR_UCC2_GETH_EN	(0x1 << 7)
+#define BCSR_UCC1_MODE_MSK	(0x3 << 4)
+#define BCSR_UCC2_MODE_MSK	(0x3 << 0)
+
+		/* Turn off UCC1 & UCC2 */
+		clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
+		clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
+
+		/* Mode is RGMII, all bits clear */
+		clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
+					 BCSR_UCC2_MODE_MSK);
+
+		/* Turn UCC1 & UCC2 on */
+		setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
+		setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
 
 		iounmap(bcsr_regs);
 	}
-- 
1.5.0.6

[PATCH 7/7] [POWERPC][SPI] spi_mpc83xx: allow use on MPC85xx

[Anton Vorontsov]

MPC85xx's QE SPI controller is almost the same comparing to MPC83xx.
Thus lets use that driver. Tested to work in loopback mode.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
 drivers/spi/Kconfig |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index b915711..14f0d0d 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -125,7 +125,7 @@ config SPI_MPC52xx_PSC
 
 config SPI_MPC83xx
 	tristate "Freescale MPC83xx SPI controller"
-	depends on SPI_MASTER && PPC_83xx && EXPERIMENTAL
+	depends on SPI_MASTER && (PPC_83xx || PPC_85xx) && EXPERIMENTAL
 	select SPI_BITBANG
 	help
 	  This enables using the Freescale MPC83xx SPI controller in master
-- 
1.5.0.6

Re: [PATCH 7/7] [POWERPC][SPI] spi_mpc83xx: allow use on MPC85xx

[Peter Korsgaard]

>>>>> "Anton" == Anton Vorontsov <avorontsov@ru.mvista.com> writes:

Hi,
 
 Anton>  config SPI_MPC83xx
 Anton>  	tristate "Freescale MPC83xx SPI controller"
 Anton> -	depends on SPI_MASTER && PPC_83xx && EXPERIMENTAL
 Anton> +	depends on SPI_MASTER && (PPC_83xx || PPC_85xx) && EXPERIMENTAL
 Anton>  	select SPI_BITBANG
 Anton>  	help
 Anton>  	  This enables using the Freescale MPC83xx SPI controller in master

Please also update the help text.

-- 
Bye, Peter Korsgaard

[PATCH v2 7/7] [POWERPC][SPI] spi_mpc83xx: allow use on MPC85xx

[Anton Vorontsov]

On Tue, Sep 25, 2007 at 04:48:00PM +0200, Peter Korsgaard wrote:
> >>>>> "Anton" == Anton Vorontsov <avorontsov@ru.mvista.com> writes:
> 
> Hi,
>  
>  Anton>  config SPI_MPC83xx
>  Anton>  	tristate "Freescale MPC83xx SPI controller"
>  Anton> -	depends on SPI_MASTER && PPC_83xx && EXPERIMENTAL
>  Anton> +	depends on SPI_MASTER && (PPC_83xx || PPC_85xx) && EXPERIMENTAL
>  Anton>  	select SPI_BITBANG
>  Anton>  	help
>  Anton>  	  This enables using the Freescale MPC83xx SPI controller in master
> 
> Please also update the help text.

Oops. Thanks, fixed.

- - - -
From: Anton Vorontsov <avorontsov@ru.mvista.com>
Subject: [PATCH v2] [POWERPC][SPI] spi_mpc83xx: allow use on MPC85xx

MPC85xx's QE SPI controller is almost the same comparing to MPC83xx.
Thus lets use that driver. Tested to work in loopback mode.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
 drivers/spi/Kconfig |   13 +++++++------
 1 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index b915711..7a7a42c 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -124,16 +124,17 @@ config SPI_MPC52xx_PSC
 	  Controller in master SPI mode.
 
 config SPI_MPC83xx
-	tristate "Freescale MPC83xx SPI controller"
-	depends on SPI_MASTER && PPC_83xx && EXPERIMENTAL
+	tristate "Freescale MPC83xx/MPC85xx SPI controller"
+	depends on SPI_MASTER && (PPC_83xx || PPC_85xx) && EXPERIMENTAL
 	select SPI_BITBANG
 	help
-	  This enables using the Freescale MPC83xx SPI controller in master
-	  mode.
+	  This enables using the Freescale MPC83xx/MPC85xx SPI controller in
+	  master mode.
 
 	  Note, this driver uniquely supports the SPI controller on the MPC83xx
-	  family of PowerPC processors.  The MPC83xx uses a simple set of shift
-	  registers for data (opposed to the CPM based descriptor model).
+	  and MPC85xx family of PowerPC processors.  The MPC83xx/MPC85xx uses a
+	  simple set of shift registers for data (opposed to the CPM based
+	  descriptor model).
 
 config SPI_OMAP_UWIRE
 	tristate "OMAP1 MicroWire"
-- 
1.5.0.6

Re: [spi-devel-general] [PATCH 7/7] [POWERPC][SPI] spi_mpc83xx: allow use on MPC85xx

[Kumar Gala]

On Sep 25, 2007, at 9:35 AM, Anton Vorontsov wrote:

> MPC85xx's QE SPI controller is almost the same comparing to MPC83xx.
> Thus lets use that driver. Tested to work in loopback mode.
>
> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
> ---
>  drivers/spi/Kconfig |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index b915711..14f0d0d 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -125,7 +125,7 @@ config SPI_MPC52xx_PSC
>
>  config SPI_MPC83xx
>  	tristate "Freescale MPC83xx SPI controller"
> -	depends on SPI_MASTER && PPC_83xx && EXPERIMENTAL
> +	depends on SPI_MASTER && (PPC_83xx || PPC_85xx) && EXPERIMENTAL
>  	select SPI_BITBANG
>  	help
>  	  This enables using the Freescale MPC83xx SPI controller in master

Should that really be just PPC_83xx || QUICC_ENGINE?

- k

Re: [spi-devel-general] [PATCH 7/7] [POWERPC][SPI] spi_mpc83xx: allow use on MPC85xx

[Anton Vorontsov]

On Tue, Sep 25, 2007 at 10:04:41AM -0500, Kumar Gala wrote:
>
> On Sep 25, 2007, at 9:35 AM, Anton Vorontsov wrote:
>
>> MPC85xx's QE SPI controller is almost the same comparing to MPC83xx.
>> Thus lets use that driver. Tested to work in loopback mode.
>>
>> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
>> ---
>>  drivers/spi/Kconfig |    2 +-
>>  1 files changed, 1 insertions(+), 1 deletions(-)
>>
>> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
>> index b915711..14f0d0d 100644
>> --- a/drivers/spi/Kconfig
>> +++ b/drivers/spi/Kconfig
>> @@ -125,7 +125,7 @@ config SPI_MPC52xx_PSC
>>
>>  config SPI_MPC83xx
>>  	tristate "Freescale MPC83xx SPI controller"
>> -	depends on SPI_MASTER && PPC_83xx && EXPERIMENTAL
>> +	depends on SPI_MASTER && (PPC_83xx || PPC_85xx) && EXPERIMENTAL
>>  	select SPI_BITBANG
>>  	help
>>  	  This enables using the Freescale MPC83xx SPI controller in master
>
> Should that really be just PPC_83xx || QUICC_ENGINE?

Well, I thought about that. By now I'm unsure if every QE
implementation will be compatible with further ones. So far
I've tested this driver on MPC8323 and MPC8568. If we'll see
more and more compatible QE SPI controllers, of course we
may just do || QUICC_ENGINE.

PPC_83xx || PPC_85xx
PPC_83xx || QUICC_ENGINE

Today first option saves us four bytes. ;-)

Re: [PATCH 4/7] [POWERPC] QE pario: support for MPC85xx layout

[Kim Phillips]

On Tue, 25 Sep 2007 18:34:40 +0400
Anton Vorontsov <avorontsov@ru.mvista.com> wrote:

> 8 bytes padding required to match MPC85xx registers layout.

<sigh>

> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>

Reviewed-by: Kim Phillips <kim.phillips@freescale.com>

Kim

Re: [spi-devel-general] [PATCH 7/7] [POWERPC][SPI] spi_mpc83xx: allow use on MPC85xx

[David Brownell]

> >> -	depends on SPI_MASTER && PPC_83xx && EXPERIMENTAL
> >> +	depends on SPI_MASTER && (PPC_83xx || PPC_85xx) && EXPERIMENTAL
> >
> > Should that really be just PPC_83xx || QUICC_ENGINE?
>
> Well, I thought about that. By now I'm unsure if every QE
> implementation will be compatible with further ones.

How many other QE implementations exist?  Is that sort of
gratuitous breakage something Freescale makes a habit of?


>	So far
> I've tested this driver on MPC8323 and MPC8568. If we'll see
> more and more compatible QE SPI controllers, of course we
> may just do || QUICC_ENGINE.
>
> PPC_83xx || PPC_85xx
> PPC_83xx || QUICC_ENGINE
>
> Today first option saves us four bytes. ;-)

It'd be good if someone would look at the relevant docs.

I'll wait for a PPC signoff before I forward this for
merge with SPI stuff...

_ Dave

Re: [spi-devel-general] [PATCH 7/7] [POWERPC][SPI] spi_mpc83xx: allow use on MPC85xx

[Kumar Gala]

On Sep 25, 2007, at 11:58 AM, David Brownell wrote:

>>>> -	depends on SPI_MASTER && PPC_83xx && EXPERIMENTAL
>>>> +	depends on SPI_MASTER && (PPC_83xx || PPC_85xx) && EXPERIMENTAL
>>>
>>> Should that really be just PPC_83xx || QUICC_ENGINE?
>>
>> Well, I thought about that. By now I'm unsure if every QE
>> implementation will be compatible with further ones.
>
> How many other QE implementations exist?  Is that sort of
> gratuitous breakage something Freescale makes a habit of?

We try not to, but HW people are know to do evil things to keep us  
software guys employed.

>> 	So far
>> I've tested this driver on MPC8323 and MPC8568. If we'll see
>> more and more compatible QE SPI controllers, of course we
>> may just do || QUICC_ENGINE.
>>
>> PPC_83xx || PPC_85xx
>> PPC_83xx || QUICC_ENGINE
>>
>> Today first option saves us four bytes. ;-)
>
> It'd be good if someone would look at the relevant docs.
>
> I'll wait for a PPC signoff before I forward this for
> merge with SPI stuff...

I'm still in favor of making it PPC_83xx || QUICC_ENGINE.

So if when we have 87xx with QUICC_ENGINE we don't have to tweak it  
again, but its a minor thing.

- k

[PATCH 7/7] [POWERPC][SPI] spi_mpc83xx: allow use on any processors with QUICC Engine

[Anton Vorontsov]

On Tue, Sep 25, 2007 at 11:00:38PM -0500, Kumar Gala wrote:
> I'm still in favor of making it PPC_83xx || QUICC_ENGINE.

Submitting... ;-)

- - - -
From: Anton Vorontsov <avorontsov@ru.mvista.com>
Subject: [POWERPC][SPI] spi_mpc83xx: allow use on any processors with QUICC Engine

Currently, all QE SPI controllers are almost the same comparing to
MPC83xx's, thus let's use that driver for them.

Tested to work on MPC85xx in loopback mode.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
 drivers/spi/Kconfig |   13 +++++++------
 1 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index b915711..a77ede5 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -124,16 +124,17 @@ config SPI_MPC52xx_PSC
 	  Controller in master SPI mode.
 
 config SPI_MPC83xx
-	tristate "Freescale MPC83xx SPI controller"
-	depends on SPI_MASTER && PPC_83xx && EXPERIMENTAL
+	tristate "Freescale MPC83xx/QUICC Engine SPI controller"
+	depends on SPI_MASTER && (PPC_83xx || QUICC_ENGINE) && EXPERIMENTAL
 	select SPI_BITBANG
 	help
-	  This enables using the Freescale MPC83xx SPI controller in master
-	  mode.
+	  This enables using the Freescale MPC83xx and QUICC Engine SPI
+	  controllers in master mode.
 
 	  Note, this driver uniquely supports the SPI controller on the MPC83xx
-	  family of PowerPC processors.  The MPC83xx uses a simple set of shift
-	  registers for data (opposed to the CPM based descriptor model).
+	  family of PowerPC processors, plus processors with QUICC Engine
+	  technology. This driver uses a simple set of shift registers for data
+	  (opposed to the CPM based descriptor model).
 
 config SPI_OMAP_UWIRE
 	tristate "OMAP1 MicroWire"
-- 
1.5.0.6

Re: [PATCH 2/7] [POWERPC] Fix QEIC->MPIC cascading

[Benjamin Herrenschmidt]

On Tue, 2007-09-25 at 18:34 +0400, Anton Vorontsov wrote:
> set_irq_chained_handler overwrites MPIC's handle_irq function
> (handle_fasteoi_irq) thus MPIC never gets eoi event from the
> cascaded IRQ. This situation hangs MPIC on MPC8568E.
> 
> Patch adds flow level "end" handler to the MPIC, and QEIC calls
> it when QEIC's interrupt processing finished.
> 
> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>

Not sure if I already NAKed it on the list, so if I didn't here's it :-)

The proper way of doing that is to have the cascade handler perform the
EOI call to mpic. Look at how it's done for i8259 mpic cascade handlers.

Basically, when doing a cascade nowadays, you can either just do a
normal request_irq() of the cascade, in which case your handler don't
have to care about the parent controller at all, but you get various
limitations and/or overhead from being a full blown interrupt handler,
or you can use the chained handler mechanism which is a "shortcut" but
implies that your cascade handler "knows" what needs to be done to the
parent (and thus is specific to the combination parent/child).

Cheers,
Ben.

Re: [PATCH 2/7] [POWERPC] Fix QEIC->MPIC cascading

[Anton Vorontsov]

On Tue, Oct 02, 2007 at 09:14:21AM +1000, Benjamin Herrenschmidt wrote:
> 
> On Tue, 2007-09-25 at 18:34 +0400, Anton Vorontsov wrote:
> > set_irq_chained_handler overwrites MPIC's handle_irq function
> > (handle_fasteoi_irq) thus MPIC never gets eoi event from the
> > cascaded IRQ. This situation hangs MPIC on MPC8568E.
> > 
> > Patch adds flow level "end" handler to the MPIC, and QEIC calls
> > it when QEIC's interrupt processing finished.
> > 
> > Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
> 
> Not sure if I already NAKed it on the list, so if I didn't here's it :-)
> 
> The proper way of doing that is to have the cascade handler perform the
> EOI call to mpic.

Exactly, this is what that patch is trying to do. QEIC cascade handler is
calling mpic's eoi() (end() actually, as it's flow level, but end == eoi.
Is it main objection? Ok, I can get rid of it, and use chip level eoi()
directly).

> Look at how it's done for i8259 mpic cascade handlers.

void pseries_8259_cascade(unsigned int irq, struct irq_desc *desc)
{       
        unsigned int cascade_irq = i8259_irq();
        if (cascade_irq != NO_IRQ)
                generic_handle_irq(cascade_irq);
        desc->chip->eoi(irq);
}
...
set_irq_chained_handler(cascade_irq, pseries_8259_cascade);

Quite similar... except that it's written in the board file.

> Basically, when doing a cascade nowadays, you can either just do a
> normal request_irq() of the cascade, in which case your handler don't
> have to care about the parent controller at all, but you get various
> limitations and/or overhead from being a full blown interrupt handler,

Though viable, but not an option.

> or you can use the chained handler mechanism which is a "shortcut" but
> implies that your cascade handler "knows" what needs to be done to the
> parent (and thus is specific to the combination parent/child).

Yup, exactly. Actually, QEIC's cascade handlers do not really know
what needs to be done, but they're good at guessing (if (chip->eoi)).

Sure, I can place board-specific QEIC handlers in the board file, but
that will be quite big code duplication for all machines using QEIC.

> Cheers,
> Ben.

Thanks,

-- 
Anton Vorontsov
email: cbou@mail.ru
backup email: ya-cbou@yandex.ru
irc://irc.freenode.net/bd2

Re: [PATCH 2/7] [POWERPC] Fix QEIC->MPIC cascading

[Benjamin Herrenschmidt]

> 
> Exactly, this is what that patch is trying to do. QEIC cascade handler is
> calling mpic's eoi() (end() actually, as it's flow level, but end == eoi.
> Is it main objection? Ok, I can get rid of it, and use chip level eoi()
> directly).

Yes, use eoi() directly, don't add end()

> Yup, exactly. Actually, QEIC's cascade handlers do not really know
> what needs to be done, but they're good at guessing (if (chip->eoi)).
> 
> Sure, I can place board-specific QEIC handlers in the board file, but
> that will be quite big code duplication for all machines using QEIC.

Maybe you can provide a set of common ones, and then just pick the one
you want from the board file ?

Or have some board code call into a QEIC init routine specifying the
type of cascade handler to use ... or whatevre you like here.

Just don't add end() where it doesn't belong.

Cheers,
Ben.

[RFC][PATCH][POWERPC] QEIC: Implement pluggable handlers, fix MPIC cascading

[Anton Vorontsov]

On Wed, Oct 03, 2007 at 08:02:42AM +1000, Benjamin Herrenschmidt wrote:
> 
> > 
> > Exactly, this is what that patch is trying to do. QEIC cascade handler is
> > calling mpic's eoi() (end() actually, as it's flow level, but end == eoi.
> > Is it main objection? Ok, I can get rid of it, and use chip level eoi()
> > directly).
> 
> Yes, use eoi() directly, don't add end()

Ok.

> > Yup, exactly. Actually, QEIC's cascade handlers do not really know
> > what needs to be done, but they're good at guessing (if (chip->eoi)).
> > 
> > Sure, I can place board-specific QEIC handlers in the board file, but
> > that will be quite big code duplication for all machines using QEIC.
> 
> Maybe you can provide a set of common ones, and then just pick the one
> you want from the board file ?
> 
> Or have some board code call into a QEIC init routine specifying the
> type of cascade handler to use ... or whatevre you like here.

Ok, thanks. How about this patch?

- - - -
From: Anton Vorontsov <avorontsov@ru.mvista.com>
Subject: [PATCH] [POWERPC] QEIC: Implement pluggable handlers, fix MPIC cascading

set_irq_chained_handler overwrites MPIC's handle_irq function
(handle_fasteoi_irq) thus MPIC never gets eoi event from the
cascaded IRQ. This situation hangs MPIC on MPC8568E.

To solve this problem efficiently, QEIC needs pluggable handlers,
specific to the underlaying interrupt controller.

Patch extends qe_ic_init() function to accept low and high interrupt
handlers. To avoid #ifdefs, stack of interrupt handlers specified in
the header file and functions are marked 'static inline', thus
handlers are compiled-in only if actually used (in the board file).
Another option would be to lookup for parent controller and
automatically detect handlers, but this will waste text size because
of never used handlers.

qe_ic_init() also changed in regard to support multiplexed high/low
lines as found in MPC8568E-MDS, plus qe_ic_cascade_muxed_mpic()
handler implemented appropriately.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
 arch/powerpc/platforms/83xx/mpc832x_mds.c |    2 +-
 arch/powerpc/platforms/83xx/mpc832x_rdb.c |    2 +-
 arch/powerpc/platforms/83xx/mpc836x_mds.c |    2 +-
 arch/powerpc/platforms/85xx/mpc85xx_mds.c |    2 +-
 arch/powerpc/sysdev/qe_lib/qe_ic.c        |   29 +++---------
 include/asm-powerpc/qe_ic.h               |   68 ++++++++++++++++++++++++++++-
 6 files changed, 78 insertions(+), 27 deletions(-)

diff --git a/arch/powerpc/platforms/83xx/mpc832x_mds.c b/arch/powerpc/platforms/83xx/mpc832x_mds.c
index d494bc4..95f32ca 100644
--- a/arch/powerpc/platforms/83xx/mpc832x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc832x_mds.c
@@ -140,7 +140,7 @@ static void __init mpc832x_sys_init_IRQ(void)
 	if (!np)
 		return;
 
-	qe_ic_init(np, 0);
+	qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
 	of_node_put(np);
 #endif				/* CONFIG_QUICC_ENGINE */
 }
diff --git a/arch/powerpc/platforms/83xx/mpc832x_rdb.c b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
index 24a790c..f842a1c 100644
--- a/arch/powerpc/platforms/83xx/mpc832x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
@@ -151,7 +151,7 @@ void __init mpc832x_rdb_init_IRQ(void)
 	if (!np)
 		return;
 
-	qe_ic_init(np, 0);
+	qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
 	of_node_put(np);
 #endif				/* CONFIG_QUICC_ENGINE */
 }
diff --git a/arch/powerpc/platforms/83xx/mpc836x_mds.c b/arch/powerpc/platforms/83xx/mpc836x_mds.c
index db69576..5971fe6 100644
--- a/arch/powerpc/platforms/83xx/mpc836x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc836x_mds.c
@@ -147,7 +147,7 @@ static void __init mpc836x_mds_init_IRQ(void)
 	if (!np)
 		return;
 
-	qe_ic_init(np, 0);
+	qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
 	of_node_put(np);
 #endif				/* CONFIG_QUICC_ENGINE */
 }
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index c379286..69c177b 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -174,7 +174,7 @@ static void __init mpc85xx_mds_pic_init(void)
 	if (!np)
 		return;
 
-	qe_ic_init(np, 0);
+	qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
 	of_node_put(np);
 #endif				/* CONFIG_QUICC_ENGINE */
 }
diff --git a/arch/powerpc/sysdev/qe_lib/qe_ic.c b/arch/powerpc/sysdev/qe_lib/qe_ic.c
index 9a2d1ed..e1c0fd6 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_ic.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_ic.c
@@ -321,25 +321,9 @@ unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
 	return irq_linear_revmap(qe_ic->irqhost, irq);
 }
 
-void qe_ic_cascade_low(unsigned int irq, struct irq_desc *desc)
-{
-	struct qe_ic *qe_ic = desc->handler_data;
-	unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
-
-	if (cascade_irq != NO_IRQ)
-		generic_handle_irq(cascade_irq);
-}
-
-void qe_ic_cascade_high(unsigned int irq, struct irq_desc *desc)
-{
-	struct qe_ic *qe_ic = desc->handler_data;
-	unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
-
-	if (cascade_irq != NO_IRQ)
-		generic_handle_irq(cascade_irq);
-}
-
-void __init qe_ic_init(struct device_node *node, unsigned int flags)
+void __init qe_ic_init(struct device_node *node, unsigned int flags,
+		void (*low_handler)(unsigned int irq, struct irq_desc *desc),
+		void (*high_handler)(unsigned int irq, struct irq_desc *desc))
 {
 	struct qe_ic *qe_ic;
 	struct resource res;
@@ -399,11 +383,12 @@ void __init qe_ic_init(struct device_node *node, unsigned int flags)
 	qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
 
 	set_irq_data(qe_ic->virq_low, qe_ic);
-	set_irq_chained_handler(qe_ic->virq_low, qe_ic_cascade_low);
+	set_irq_chained_handler(qe_ic->virq_low, low_handler);
 
-	if (qe_ic->virq_high != NO_IRQ) {
+	if (qe_ic->virq_high != NO_IRQ &&
+			qe_ic->virq_high != qe_ic->virq_low) {
 		set_irq_data(qe_ic->virq_high, qe_ic);
-		set_irq_chained_handler(qe_ic->virq_high, qe_ic_cascade_high);
+		set_irq_chained_handler(qe_ic->virq_high, high_handler);
 	}
 }
 
diff --git a/include/asm-powerpc/qe_ic.h b/include/asm-powerpc/qe_ic.h
index e386fb7..a779b2c 100644
--- a/include/asm-powerpc/qe_ic.h
+++ b/include/asm-powerpc/qe_ic.h
@@ -56,9 +56,75 @@ enum qe_ic_grp_id {
 	QE_IC_GRP_RISCB		/* QE interrupt controller RISC group B */
 };
 
-void qe_ic_init(struct device_node *node, unsigned int flags);
+void qe_ic_init(struct device_node *node, unsigned int flags,
+		void (*low_handler)(unsigned int irq, struct irq_desc *desc),
+		void (*high_handler)(unsigned int irq, struct irq_desc *desc));
 void qe_ic_set_highest_priority(unsigned int virq, int high);
 int qe_ic_set_priority(unsigned int virq, unsigned int priority);
 int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);
 
+struct qe_ic;
+unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic);
+unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic);
+
+static inline void qe_ic_cascade_low_ipic(unsigned int irq,
+					  struct irq_desc *desc)
+{
+	struct qe_ic *qe_ic = desc->handler_data;
+	unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
+
+	if (cascade_irq != NO_IRQ)
+		generic_handle_irq(cascade_irq);
+}
+
+static inline void qe_ic_cascade_high_ipic(unsigned int irq,
+					   struct irq_desc *desc)
+{
+	struct qe_ic *qe_ic = desc->handler_data;
+	unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
+
+	if (cascade_irq != NO_IRQ)
+		generic_handle_irq(cascade_irq);
+}
+
+static inline void qe_ic_cascade_low_mpic(unsigned int irq,
+					  struct irq_desc *desc)
+{
+	struct qe_ic *qe_ic = desc->handler_data;
+	unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
+
+	if (cascade_irq != NO_IRQ)
+		generic_handle_irq(cascade_irq);
+
+	desc->chip->eoi(irq);
+}
+
+static inline void qe_ic_cascade_high_mpic(unsigned int irq,
+					   struct irq_desc *desc)
+{
+	struct qe_ic *qe_ic = desc->handler_data;
+	unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
+
+	if (cascade_irq != NO_IRQ)
+		generic_handle_irq(cascade_irq);
+
+	desc->chip->eoi(irq);
+}
+
+static inline void qe_ic_cascade_muxed_mpic(unsigned int irq,
+					    struct irq_desc *desc)
+{
+	struct qe_ic *qe_ic = desc->handler_data;
+	unsigned int cascade_irq;
+
+	cascade_irq = qe_ic_get_high_irq(qe_ic);
+	if (cascade_irq == NO_IRQ)
+		cascade_irq = qe_ic_get_low_irq(qe_ic);
+
+	if (cascade_irq != NO_IRQ)
+		generic_handle_irq(cascade_irq);
+
+	desc->chip->eoi(irq);
+}
+
 #endif /* _ASM_POWERPC_QE_IC_H */
-- 
1.5.0.6

Re: [RFC][PATCH][POWERPC] QEIC: Implement pluggable handlers, fix MPIC cascading

[Benjamin Herrenschmidt]

> From: Anton Vorontsov <avorontsov@ru.mvista.com>
> Subject: [PATCH] [POWERPC] QEIC: Implement pluggable handlers, fix MPIC cascading
> 
> set_irq_chained_handler overwrites MPIC's handle_irq function
> (handle_fasteoi_irq) thus MPIC never gets eoi event from the
> cascaded IRQ. This situation hangs MPIC on MPC8568E.
> 
> To solve this problem efficiently, QEIC needs pluggable handlers,
> specific to the underlaying interrupt controller.
> 
> Patch extends qe_ic_init() function to accept low and high interrupt
> handlers. To avoid #ifdefs, stack of interrupt handlers specified in
> the header file and functions are marked 'static inline', thus
> handlers are compiled-in only if actually used (in the board file).
> Another option would be to lookup for parent controller and
> automatically detect handlers, but this will waste text size because
> of never used handlers.
> 
> qe_ic_init() also changed in regard to support multiplexed high/low
> lines as found in MPC8568E-MDS, plus qe_ic_cascade_muxed_mpic()
> handler implemented appropriately.
> 
> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>

Looks allright, if it also works, then ship it :-)

Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

> ---
>  arch/powerpc/platforms/83xx/mpc832x_mds.c |    2 +-
>  arch/powerpc/platforms/83xx/mpc832x_rdb.c |    2 +-
>  arch/powerpc/platforms/83xx/mpc836x_mds.c |    2 +-
>  arch/powerpc/platforms/85xx/mpc85xx_mds.c |    2 +-
>  arch/powerpc/sysdev/qe_lib/qe_ic.c        |   29 +++---------
>  include/asm-powerpc/qe_ic.h               |   68 ++++++++++++++++++++++++++++-
>  6 files changed, 78 insertions(+), 27 deletions(-)
> 
> diff --git a/arch/powerpc/platforms/83xx/mpc832x_mds.c b/arch/powerpc/platforms/83xx/mpc832x_mds.c
> index d494bc4..95f32ca 100644
> --- a/arch/powerpc/platforms/83xx/mpc832x_mds.c
> +++ b/arch/powerpc/platforms/83xx/mpc832x_mds.c
> @@ -140,7 +140,7 @@ static void __init mpc832x_sys_init_IRQ(void)
>  	if (!np)
>  		return;
>  
> -	qe_ic_init(np, 0);
> +	qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
>  	of_node_put(np);
>  #endif				/* CONFIG_QUICC_ENGINE */
>  }
> diff --git a/arch/powerpc/platforms/83xx/mpc832x_rdb.c b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
> index 24a790c..f842a1c 100644
> --- a/arch/powerpc/platforms/83xx/mpc832x_rdb.c
> +++ b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
> @@ -151,7 +151,7 @@ void __init mpc832x_rdb_init_IRQ(void)
>  	if (!np)
>  		return;
>  
> -	qe_ic_init(np, 0);
> +	qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
>  	of_node_put(np);
>  #endif				/* CONFIG_QUICC_ENGINE */
>  }
> diff --git a/arch/powerpc/platforms/83xx/mpc836x_mds.c b/arch/powerpc/platforms/83xx/mpc836x_mds.c
> index db69576..5971fe6 100644
> --- a/arch/powerpc/platforms/83xx/mpc836x_mds.c
> +++ b/arch/powerpc/platforms/83xx/mpc836x_mds.c
> @@ -147,7 +147,7 @@ static void __init mpc836x_mds_init_IRQ(void)
>  	if (!np)
>  		return;
>  
> -	qe_ic_init(np, 0);
> +	qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
>  	of_node_put(np);
>  #endif				/* CONFIG_QUICC_ENGINE */
>  }
> diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
> index c379286..69c177b 100644
> --- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
> +++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
> @@ -174,7 +174,7 @@ static void __init mpc85xx_mds_pic_init(void)
>  	if (!np)
>  		return;
>  
> -	qe_ic_init(np, 0);
> +	qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
>  	of_node_put(np);
>  #endif				/* CONFIG_QUICC_ENGINE */
>  }
> diff --git a/arch/powerpc/sysdev/qe_lib/qe_ic.c b/arch/powerpc/sysdev/qe_lib/qe_ic.c
> index 9a2d1ed..e1c0fd6 100644
> --- a/arch/powerpc/sysdev/qe_lib/qe_ic.c
> +++ b/arch/powerpc/sysdev/qe_lib/qe_ic.c
> @@ -321,25 +321,9 @@ unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
>  	return irq_linear_revmap(qe_ic->irqhost, irq);
>  }
>  
> -void qe_ic_cascade_low(unsigned int irq, struct irq_desc *desc)
> -{
> -	struct qe_ic *qe_ic = desc->handler_data;
> -	unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
> -
> -	if (cascade_irq != NO_IRQ)
> -		generic_handle_irq(cascade_irq);
> -}
> -
> -void qe_ic_cascade_high(unsigned int irq, struct irq_desc *desc)
> -{
> -	struct qe_ic *qe_ic = desc->handler_data;
> -	unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
> -
> -	if (cascade_irq != NO_IRQ)
> -		generic_handle_irq(cascade_irq);
> -}
> -
> -void __init qe_ic_init(struct device_node *node, unsigned int flags)
> +void __init qe_ic_init(struct device_node *node, unsigned int flags,
> +		void (*low_handler)(unsigned int irq, struct irq_desc *desc),
> +		void (*high_handler)(unsigned int irq, struct irq_desc *desc))
>  {
>  	struct qe_ic *qe_ic;
>  	struct resource res;
> @@ -399,11 +383,12 @@ void __init qe_ic_init(struct device_node *node, unsigned int flags)
>  	qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
>  
>  	set_irq_data(qe_ic->virq_low, qe_ic);
> -	set_irq_chained_handler(qe_ic->virq_low, qe_ic_cascade_low);
> +	set_irq_chained_handler(qe_ic->virq_low, low_handler);
>  
> -	if (qe_ic->virq_high != NO_IRQ) {
> +	if (qe_ic->virq_high != NO_IRQ &&
> +			qe_ic->virq_high != qe_ic->virq_low) {
>  		set_irq_data(qe_ic->virq_high, qe_ic);
> -		set_irq_chained_handler(qe_ic->virq_high, qe_ic_cascade_high);
> +		set_irq_chained_handler(qe_ic->virq_high, high_handler);
>  	}
>  }
>  
> diff --git a/include/asm-powerpc/qe_ic.h b/include/asm-powerpc/qe_ic.h
> index e386fb7..a779b2c 100644
> --- a/include/asm-powerpc/qe_ic.h
> +++ b/include/asm-powerpc/qe_ic.h
> @@ -56,9 +56,75 @@ enum qe_ic_grp_id {
>  	QE_IC_GRP_RISCB		/* QE interrupt controller RISC group B */
>  };
>  
> -void qe_ic_init(struct device_node *node, unsigned int flags);
> +void qe_ic_init(struct device_node *node, unsigned int flags,
> +		void (*low_handler)(unsigned int irq, struct irq_desc *desc),
> +		void (*high_handler)(unsigned int irq, struct irq_desc *desc));
>  void qe_ic_set_highest_priority(unsigned int virq, int high);
>  int qe_ic_set_priority(unsigned int virq, unsigned int priority);
>  int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);
>  
> +struct qe_ic;
> +unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic);
> +unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic);
> +
> +static inline void qe_ic_cascade_low_ipic(unsigned int irq,
> +					  struct irq_desc *desc)
> +{
> +	struct qe_ic *qe_ic = desc->handler_data;
> +	unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
> +
> +	if (cascade_irq != NO_IRQ)
> +		generic_handle_irq(cascade_irq);
> +}
> +
> +static inline void qe_ic_cascade_high_ipic(unsigned int irq,
> +					   struct irq_desc *desc)
> +{
> +	struct qe_ic *qe_ic = desc->handler_data;
> +	unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
> +
> +	if (cascade_irq != NO_IRQ)
> +		generic_handle_irq(cascade_irq);
> +}
> +
> +static inline void qe_ic_cascade_low_mpic(unsigned int irq,
> +					  struct irq_desc *desc)
> +{
> +	struct qe_ic *qe_ic = desc->handler_data;
> +	unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
> +
> +	if (cascade_irq != NO_IRQ)
> +		generic_handle_irq(cascade_irq);
> +
> +	desc->chip->eoi(irq);
> +}
> +
> +static inline void qe_ic_cascade_high_mpic(unsigned int irq,
> +					   struct irq_desc *desc)
> +{
> +	struct qe_ic *qe_ic = desc->handler_data;
> +	unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
> +
> +	if (cascade_irq != NO_IRQ)
> +		generic_handle_irq(cascade_irq);
> +
> +	desc->chip->eoi(irq);
> +}
> +
> +static inline void qe_ic_cascade_muxed_mpic(unsigned int irq,
> +					    struct irq_desc *desc)
> +{
> +	struct qe_ic *qe_ic = desc->handler_data;
> +	unsigned int cascade_irq;
> +
> +	cascade_irq = qe_ic_get_high_irq(qe_ic);
> +	if (cascade_irq == NO_IRQ)
> +		cascade_irq = qe_ic_get_low_irq(qe_ic);
> +
> +	if (cascade_irq != NO_IRQ)
> +		generic_handle_irq(cascade_irq);
> +
> +	desc->chip->eoi(irq);
> +}
> +
>  #endif /* _ASM_POWERPC_QE_IC_H */

Re: [PATCH 4/7] [POWERPC] QE pario: support for MPC85xx layout

[Kumar Gala]

On Sep 25, 2007, at 9:34 AM, Anton Vorontsov wrote:

> 8 bytes padding required to match MPC85xx registers layout.
>
> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
> ---
>  arch/powerpc/sysdev/qe_lib/qe_io.c |    3 +++
>  1 files changed, 3 insertions(+), 0 deletions(-)
>
> diff --git a/arch/powerpc/sysdev/qe_lib/qe_io.c b/arch/powerpc/ 
> sysdev/qe_lib/qe_io.c
> index e32b45b..d566e89 100644
> --- a/arch/powerpc/sysdev/qe_lib/qe_io.c
> +++ b/arch/powerpc/sysdev/qe_lib/qe_io.c
> @@ -36,6 +36,9 @@ struct port_regs {
>  	__be32	cpdir2;		/* Direction register */
>  	__be32	cppar1;		/* Pin assignment register */
>  	__be32	cppar2;		/* Pin assignment register */
> +#ifdef CONFIG_MPC85xx

use CONFIG_PPC_85xx

> +	u8	pad[8];
> +#endif
>  };

- k

Re: [RFC][PATCH][POWERPC] QEIC: Implement pluggable handlers, fix MPIC cascading

[Kumar Gala]

On Oct 4, 2007, at 5:05 PM, Benjamin Herrenschmidt wrote:

>
>> From: Anton Vorontsov <avorontsov@ru.mvista.com>
>> Subject: [PATCH] [POWERPC] QEIC: Implement pluggable handlers, fix  
>> MPIC cascading
>>
>> set_irq_chained_handler overwrites MPIC's handle_irq function
>> (handle_fasteoi_irq) thus MPIC never gets eoi event from the
>> cascaded IRQ. This situation hangs MPIC on MPC8568E.
>>
>> To solve this problem efficiently, QEIC needs pluggable handlers,
>> specific to the underlaying interrupt controller.
>>
>> Patch extends qe_ic_init() function to accept low and high interrupt
>> handlers. To avoid #ifdefs, stack of interrupt handlers specified in
>> the header file and functions are marked 'static inline', thus
>> handlers are compiled-in only if actually used (in the board file).
>> Another option would be to lookup for parent controller and
>> automatically detect handlers, but this will waste text size because
>> of never used handlers.
>>
>> qe_ic_init() also changed in regard to support multiplexed high/low
>> lines as found in MPC8568E-MDS, plus qe_ic_cascade_muxed_mpic()
>> handler implemented appropriately.
>>
>> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
>
> Looks allright, if it also works, then ship it :-)
>
> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

Now that this has been ack'd by Ben if you can respin the patch set  
we can get these in for 2.6.24

(I assume you are using a UCC as ethernet for test some of the QE  
support on 8568?)

- k

Re: [RFC][PATCH][POWERPC] QEIC: Implement pluggable handlers, fix MPIC cascading

[Anton Vorontsov]

On Fri, Oct 05, 2007 at 12:18:58AM -0500, Kumar Gala wrote:
[...]
>>> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
>>
>> Looks allright, if it also works, then ship it :-)
>>
>> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> Now that this has been ack'd by Ben if you can respin the patch set we can 
> get these in for 2.6.24

Great, will do.

> (I assume you are using a UCC as ethernet for test some of the QE support 
> on 8568?)

Yup, UCC as eth. Plus I've also tested SPI (which is in QE) in
loopback mode.

Thanks,

-- 
Anton Vorontsov
email: cbou@mail.ru
backup email: ya-cbou@yandex.ru
irc://irc.freenode.net/bd2

[PATCH 7/7] [POWERPC][SPI] spi_mpc83xx: allow use on any processors with QUICC Engine

[Anton Vorontsov]

Currently, all QE SPI controllers are almost the same comparing to
MPC83xx's, thus let's use that driver for them.

Tested to work on MPC85xx in loopback mode.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---

This is respin. Hope this time it will get ack from the
PowerPC team.

 drivers/spi/Kconfig |   13 +++++++------
 1 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index b915711..a77ede5 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -124,16 +124,17 @@ config SPI_MPC52xx_PSC
 	  Controller in master SPI mode.
 
 config SPI_MPC83xx
-	tristate "Freescale MPC83xx SPI controller"
-	depends on SPI_MASTER && PPC_83xx && EXPERIMENTAL
+	tristate "Freescale MPC83xx/QUICC Engine SPI controller"
+	depends on SPI_MASTER && (PPC_83xx || QUICC_ENGINE) && EXPERIMENTAL
 	select SPI_BITBANG
 	help
-	  This enables using the Freescale MPC83xx SPI controller in master
-	  mode.
+	  This enables using the Freescale MPC83xx and QUICC Engine SPI
+	  controllers in master mode.
 
 	  Note, this driver uniquely supports the SPI controller on the MPC83xx
-	  family of PowerPC processors.  The MPC83xx uses a simple set of shift
-	  registers for data (opposed to the CPM based descriptor model).
+	  family of PowerPC processors, plus processors with QUICC Engine
+	  technology. This driver uses a simple set of shift registers for data
+	  (opposed to the CPM based descriptor model).
 
 config SPI_OMAP_UWIRE
 	tristate "OMAP1 MicroWire"
-- 
1.5.0.6