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From: Josh Boyer <jwboyer@linux.vnet.ibm.com>
To: Jeff Mock <jeff@mock.com>
Cc: linuxppc-embedded@ozlabs.org
Subject: Re: PPC440EPx GPIO control help
Date: Wed, 17 Oct 2007 15:41:09 -0500	[thread overview]
Message-ID: <20071017154109.0c6a826e@weaponx.rchland.ibm.com> (raw)
In-Reply-To: <47167002.7060202@mock.com>

On Wed, 17 Oct 2007 13:26:42 -0700
Jeff Mock <jeff@mock.com> wrote:

> 
> 
> Josh Boyer wrote:
> > On Tue, 2007-10-16 at 23:21 -0700, Jeff Mock wrote:
> >> David Hawkins wrote:
> >>>> I have a PPC440EPx Sequoia Evaluation board that runs on Linux 2.6.21. 
> >>>> What I would want to do is to control (write and read values to) its 
> >>>> GPIO. Perhaps similar to Turbo C's outputb(0x378,0x01) to write and 
> >>>> inportb(0x378) to read. I read the PPC440EPx manual but I find it 
> >>>> difficult to understand.
> >>>>
> >>>> Could anyone show me any tutorial or some sample codes?
> >>> I copied the code below from some test code I wrote for a TS7300
> >>> board (uses an ARM EP9302 processor). However, since its user-space
> >>> code it should work fine.
> >>>
> >> I might be a little out of date, but I think you must write your own 
> >> driver to wiggle the GPIO pins on a 440 processor.  I just finished a 
> >> project using a 440GX with a 2.6.15 kernel (we froze the code about 8 
> >> months ago).
> >>
> >> The 440 powerPC core is a 32-bit processor with 36-bit physical 
> >> addresses.  The physical address for the GPIO pins is someplace above 
> >> 4GB.  An mmap() of /dev/mem only lets you map the lower 4GB of the 
> >> address space, as a result you can't write a user space program on the 
> >> 440 to wiggle the GPIO pins.  (This was true with 2.6.15, I can't speak 
> >> for later kernels).
> > 
> > This depends on the 440 chip itself.  If I recall correctly, the
> > 440EP(x) chips don't have I/O above 4GB.
> > 
> 
> At first I thought you were right, I remember something about the 440GX 
> being the weird processor with I/O mapped above 4GB.  I just took a look 
> at the 440EPx datasheet on the AMCC website and it looks like the GPIO 
> registers are mapped above 4GB:
> 
>     GPIO0 controller       1 EF60 0B00
>     GPIO1 controller       1 EF60 0C00

Actually, it's 440EP that has the addresses below 4GB, not 440EPx.  My
apologies for the confusion.  As far as "weird" goes in the 44x world,
440EP is the oddball as I believe most all other 44x versions have some
if not all I/O above 4GB.

josh

  reply	other threads:[~2007-10-17 20:41 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2007-10-17  3:29 PPC440EPx GPIO control help Dell Query
2007-10-17  4:15 ` David Hawkins
2007-10-17  6:21   ` Jeff Mock
2007-10-17 10:49     ` Josh Boyer
2007-10-17 12:17       ` Misbah khan
2007-10-17 20:26       ` Jeff Mock
2007-10-17 20:41         ` Josh Boyer [this message]
2007-10-17 16:19     ` David Hawkins
2007-10-18  2:05       ` Dell Query
2007-10-18  2:00     ` Dell Query
2007-10-18  3:22       ` Jeff Mock
  -- strict thread matches above, loose matches on Subject: below --
2007-10-17  3:14 Dell Query

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