From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.semihalf.com (mail.semihalf.com [83.12.36.68]) by ozlabs.org (Postfix) with ESMTP id D78FCDDF7F for ; Wed, 24 Oct 2007 09:13:58 +1000 (EST) Received: from localhost (unknown [127.0.0.1]) by mail.semihalf.com (Postfix) with ESMTP id A485E14311 for ; Wed, 24 Oct 2007 01:13:58 +0200 (CEST) Received: from mail.semihalf.com ([127.0.0.1]) by localhost (mail.semihalf.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 08109-05 for ; Wed, 24 Oct 2007 01:13:56 +0200 (CEST) Received: from hekate.izotz.org (frozen.izotz.org [83.175.187.135]) by mail.semihalf.com (Postfix) with ESMTP id B1069142C1 for ; Wed, 24 Oct 2007 01:13:56 +0200 (CEST) From: Marian Balakowicz Subject: [PATCH 05/11] [POWERPC] TQM5200 DTS To: linuxppc-dev@ozlabs.org Date: Wed, 24 Oct 2007 01:13:33 +0200 Message-ID: <20071023231333.29359.35252.stgit@hekate.izotz.org> In-Reply-To: <20071023231302.29359.27417.stgit@hekate.izotz.org> References: <20071023231302.29359.27417.stgit@hekate.izotz.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Add device tree source file for TQM5200 board. Signed-off-by: Marian Balakowicz --- arch/powerpc/boot/dts/tqm5200.dts | 236 +++++++++++++++++++++++++++++++++++++ 1 files changed, 236 insertions(+), 0 deletions(-) create mode 100644 arch/powerpc/boot/dts/tqm5200.dts diff --git a/arch/powerpc/boot/dts/tqm5200.dts b/arch/powerpc/boot/dts/tqm5200.dts new file mode 100644 index 0000000..01c7778 --- /dev/null +++ b/arch/powerpc/boot/dts/tqm5200.dts @@ -0,0 +1,236 @@ +/* + * TQM5200 board Device Tree Source + * + * Copyright (C) 2007 Semihalf + * Marian Balakowicz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/* + * WARNING: Do not depend on this tree layout remaining static just yet. + * The MPC5200 device tree conventions are still in flux + * Keep an eye on the linuxppc-dev mailing list for more details + */ + +/ { + model = "tqc,tqm5200"; + compatible = "tqc,tqm5200","generic-mpc5200"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,5200@0 { + device_type = "cpu"; + reg = <0>; + d-cache-line-size = <20>; + i-cache-line-size = <20>; + d-cache-size = <4000>; // L1, 16K + i-cache-size = <4000>; // L1, 16K + timebase-frequency = <0>; // from bootloader + bus-frequency = <0>; // from bootloader + clock-frequency = <0>; // from bootloader + }; + }; + + memory { + device_type = "memory"; + reg = <00000000 04000000>; // 64MB + }; + + soc5200@f0000000 { + model = "fsl,mpc5200"; + compatible = "mpc5200"; + revision = ""; // from bootloader + device_type = "soc"; + ranges = <0 f0000000 0000c000>; + reg = ; + bus-frequency = <0>; // from bootloader + system-frequency = <0>; // from bootloader + + cdm@200 { + compatible = "mpc5200-cdm"; + reg = <200 38>; + }; + + mpc5200_pic: pic@500 { + // 5200 interrupts are encoded into two levels; + interrupt-controller; + #interrupt-cells = <3>; + device_type = "interrupt-controller"; + compatible = "mpc5200-pic"; + reg = <500 80>; + }; + + gpt@600 { // General Purpose Timer + compatible = "fsl,mpc5200-gpt"; + cell-index = <0>; + reg = <600 10>; + interrupts = <1 9 0>; + interrupt-parent = <&mpc5200_pic>; + fsl,has-wdt; + }; + + gpio@b00 { + compatible = "mpc5200-gpio"; + reg = ; + interrupts = <1 7 0>; + interrupt-parent = <&mpc5200_pic>; + }; + + usb@1000 { + device_type = "usb-ohci-be"; + compatible = "mpc5200-ohci","ohci-be"; + reg = <1000 ff>; + interrupts = <2 6 0>; + interrupt-parent = <&mpc5200_pic>; + }; + + dma-controller@1200 { + compatible = "mpc5200-bestcomm"; + reg = <1200 80>; + interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 + 3 4 0 3 5 0 3 6 0 3 7 0 + 3 8 0 3 9 0 3 a 0 3 b 0 + 3 c 0 3 d 0 3 e 0 3 f 0>; + interrupt-parent = <&mpc5200_pic>; + }; + + xlb@1f00 { + compatible = "mpc5200-xlb"; + reg = <1f00 100>; + }; + + serial@2000 { // PSC1 + device_type = "serial"; + compatible = "mpc5200-psc-uart"; + port-number = <0>; // Logical port assignment + cell-index = <0>; + reg = <2000 100>; + interrupts = <2 1 0>; + interrupt-parent = <&mpc5200_pic>; + }; + + serial@2200 { // PSC2 + device_type = "serial"; + compatible = "mpc5200-psc-uart"; + port-number = <1>; // Logical port assignment + cell-index = <1>; + reg = <2200 100>; + interrupts = <2 2 0>; + interrupt-parent = <&mpc5200_pic>; + }; + + serial@2400 { // PSC3 + device_type = "serial"; + compatible = "mpc5200-psc-uart"; + port-number = <2>; // Logical port assignment + cell-index = <2>; + reg = <2400 100>; + interrupts = <2 3 0>; + interrupt-parent = <&mpc5200_pic>; + }; + + ethernet@3000 { + device_type = "network"; + compatible = "mpc5200-fec"; + reg = <3000 800>; + local-mac-address = [ 00 00 00 00 00 00 ]; /* Filled in by U-Boot */ + interrupts = <2 5 0>; + interrupt-parent = <&mpc5200_pic>; + }; + + ata@3a00 { + device_type = "ata"; + compatible = "mpc5200-ata"; + reg = <3a00 100>; + interrupts = <2 7 0>; + interrupt-parent = <&mpc5200_pic>; + }; + + i2c@3d40 { + device_type = "i2c"; + compatible = "mpc5200-i2c","fsl-i2c"; + reg = <3d40 40>; + interrupts = <2 10 0>; + interrupt-parent = <&mpc5200_pic>; + fsl5200-clocking; + }; + + sram@8000 { + compatible = "mpc5200-sram","sram"; + reg = <8000 4000>; + }; + }; + + lpb@fc000000 { + model = "fsl,lpb"; + compatible = "lpb"; + device_type = "lpb"; + ranges = <0 fc000000 02000000>; + + flash@00000000 { + compatible = "cfi-flash"; + reg = <00000000 02000000>; + bank-width = <4>; + device-width = <2>; + #size-cells = <1>; + #address-cells = <1>; + partition@0 { + label = "firmware"; + reg = <0 a0000>; + }; + partition@a0000 { + label = "dtb"; + reg = ; + }; + partition@c0000 { + label = "kernel"; + reg = ; + }; + partition@300000 { + label = "initrd"; + reg = <300000 200000>; + }; + partition@500000 { + label = "small-fs"; + reg = <500000 400000>; + }; + partition@900000 { + label = "misc"; + reg = <900000 800000>; + }; + partition@1100000 { + label = "big-fs"; + reg = <1100000 f00000>; + }; + }; + }; + + pci@f0000d00 { + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + compatible = "fsl,mpc5200-pci"; + reg = ; + interrupt-map-mask = ; + interrupt-map = ; + clock-frequency = <0>; // From boot loader + interrupts = <2 8 0 2 9 0 2 a 0>; + interrupt-parent = <&mpc5200_pic>; + bus-range = <0 0>; + ranges = <42000000 0 80000000 80000000 0 10000000 + 02000000 0 90000000 90000000 0 10000000 + 01000000 0 00000000 a0000000 0 01000000>; + }; +};