From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from de01egw01.freescale.net (de01egw01.freescale.net [192.88.165.102]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "de01egw01.freescale.net", Issuer "Thawte Premium Server CA" (verified OK)) by ozlabs.org (Postfix) with ESMTP id E53B5DDDF2 for ; Tue, 20 Nov 2007 12:04:51 +1100 (EST) Date: Mon, 19 Nov 2007 19:04:43 -0600 From: Kim Phillips To: Kumar Gala , linuxppc-dev@ozlabs.org Subject: [PATCH] powerpc: mpc832x mds: Fix board PHY reset code Message-Id: <20071119190443.7c04ae6b.kim.phillips@freescale.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Cc: Li Yang , peter.vanackeren@freescale.com List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , currently the board-level PHY reset code for the mpc832x MDS messes with reset configuration words source settings which is plain wrong (it looks like this board code was cut-n-pasted from the mpc8360 mds code, which has the PHY reset bits in a different BCSR); this patch points the PHY reset code to the proper mpc832x mds PHY reset bits in the BCSR. Signed-off-by: Peter Van Ackeren Signed-off-by: Kim Phillips --- arch/powerpc/platforms/83xx/mpc832x_mds.c | 7 ++++--- 1 files changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/platforms/83xx/mpc832x_mds.c b/arch/powerpc/platforms/83xx/mpc832x_mds.c index 972fa85..9e3bfcc 100644 --- a/arch/powerpc/platforms/83xx/mpc832x_mds.c +++ b/arch/powerpc/platforms/83xx/mpc832x_mds.c @@ -90,10 +90,11 @@ static void __init mpc832x_sys_setup_arch(void) if ((np = of_find_compatible_node(NULL, "network", "ucc_geth")) != NULL){ - /* Reset the Ethernet PHY */ - bcsr_regs[9] &= ~0x20; + /* Reset the Ethernet PHYs */ +#define BCSR8_FETH_RST 0x50 + bcsr_regs[8] &= ~BCSR8_FETH_RST; udelay(1000); - bcsr_regs[9] |= 0x20; + bcsr_regs[8] |= BCSR8_FETH_RST; iounmap(bcsr_regs); of_node_put(np); } -- 1.5.2.2