From: Eugene Surovegin <ebs@ebshome.net>
To: Yuri Tikhonov <yur@emcraft.com>
Cc: linuxppc-dev@ozlabs.org, sr@denx.de, dzu@denx.de
Subject: Re: [PATCH 0/2] [PPC 4xx] L2-cache synchronization for ppc44x
Date: Wed, 28 Nov 2007 11:50:37 -0800 [thread overview]
Message-ID: <20071128195037.GB22325@gate.ebshome.net> (raw)
In-Reply-To: <7310408706.20071107014010@emcraft.com>
On Wed, Nov 07, 2007 at 01:40:10AM +0300, Yuri Tikhonov wrote:
>
> Hello all,
>
> Here is a patch-set for support L2-cache synchronization routines for
> the ppc44x processors family. I know that the "ppc" branch is for bug-fixing only, thus
> the patch-set is just FYI [though enabled but non-coherent L2-cache may appear as a bug for
> someone who uses one of the boards listed below :)].
>
> [PATCH 1/2] [PPC 4xx] invalidate_l2cache_range() implementation for ppc44x;
> [PATCH 2/2] [PPC 44x] enable L2-cache for the following ppc44x-based boards: ALPR,
> Katmai, Ocotea, and Taishan.
Why is this all needed?
IIRC ibm440gx_l2c_enable() configures 64G snoop region for L2C.
Did AMCC made non-only-coherent L2C chips recently?
--
Eugene
next prev parent reply other threads:[~2007-11-28 19:57 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-11-06 22:40 [PATCH 0/2] [PPC 4xx] L2-cache synchronization for ppc44x Yuri Tikhonov
2007-11-28 19:50 ` Eugene Surovegin [this message]
2008-01-11 15:24 ` Yuri Tikhonov
2008-01-11 17:41 ` Eugene Surovegin
2008-01-11 22:05 ` Benjamin Herrenschmidt
2008-01-11 22:38 ` Eugene Surovegin
2008-01-12 1:52 ` Benjamin Herrenschmidt
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