[PATCH 1/5] PowerPC 74xx: Katana Qp device tree

[PATCH 1/5] PowerPC 74xx: Katana Qp device tree

[Andrei Dolnikov]

Device tree source file for the Emerson Katana Qp board

Signed-off-by: Andrei Dolnikov <adolnikov@ru.mvisa.com>

---
 arch/powerpc/boot/dts/katanaqp.dts |  357 +++++++++++++++++++++++++++++++++++++
 1 files changed, 357 insertions(+)

diff --git a/arch/powerpc/boot/dts/katanaqp.dts b/arch/powerpc/boot/dts/katanaqp.dts
new file mode 100644
index 0000000..9273c4e
--- /dev/null
+++ b/arch/powerpc/boot/dts/katanaqp.dts
@@ -0,0 +1,357 @@
+/* Device Tree Source for Emerson Katana Qp
+ *
+ * Authors: Vladislav Buzov <vbuzov@ru.mvista.com>
+ *	    Andrei Dolnikov <adolnikov@ru.mvista.com>
+ * 
+ * Based on prpmc8200.dts by Mark A. Greer <mgreer@mvista.com>
+ *
+ * 2007 (c) MontaVista, Software, Inc.  This file is licensed under
+ * the terms of the GNU General Public License version 2.  This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ */
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	model = "Katana-Qp"; /* Default */
+	compatible = "emerson,Katana-Qp";
+	coherency-off;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,7448@0 {
+			device_type = "cpu";
+			reg = <0>;
+			clock-frequency = <0>;		/* From U-boot */
+			bus-frequency = <0>;		/* From U-boot */
+			timebase-frequency = <0>;	/* From U-boot */
+			i-cache-line-size = <20>;
+			d-cache-line-size = <20>;
+			i-cache-size = <8000>;
+			d-cache-size = <8000>;
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <00000000 20000000>;	/* Default (512MB) */
+	};
+
+	mv64x60@f8100000 { /* Marvell Discovery */
+		#address-cells = <1>;
+		#size-cells = <1>;
+		model = "mv64460";			/* Default */
+		compatible = "marvell,mv64x60";
+		clock-frequency = <7f28155>;		/* 133.333333 MHz */
+		reg = <f8100000 00010000>;
+		virtual-reg = <f8100000>;
+		ranges = <c1000000 c1000000 01000000	/* PCI 1 I/O Space */
+			  90000000 90000000 30000000	/* PCI 1 MEM Space */
+			  e8000000 e8000000 04000000	/* User FLASH: Up to 64Mb */
+			  00000000 f8100000 00010000	/* Bridge's regs */
+			  f8500000 f8500000 00040000>;	/* Integrated SRAM */
+
+		flash@e8000000 {
+			compatible = "cfi-flash";
+			reg = <e8000000 1000000>; /* Default (16MB) */
+			probe-type = "CFI";
+			bank-width = <4>;
+			
+			partition@0 {
+				label = "Primary Monitor";
+				reg = <0 100000>; /* 1Mb */
+				read-only;
+			};
+
+			partition@100000 {
+				label = "Primary Kernel";
+				reg = <100000 200000>; /* 2 Mb */
+			};
+
+			partition@300000 {
+				label = "Primary FS";
+				reg = <300000 d00000>; /* 13 Mb */
+			};
+
+		};
+
+		cpld@f8200000 {
+			compatible = "altera,maxii";
+			reg = <f8200000 40000>;
+			virtual-reg = <f8200000>;
+		};
+
+		mdio {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "marvell,mv64x60-mdio";
+			ethernet-phy@0 {
+				block-index = <0>;
+				compatible = "marvell,mv88e1111";
+				reg = <a>;
+			};
+			ethernet-phy@1 {
+				compatible = "marvell,mv88e1111";
+				block-index = <1>;
+				reg = <d>;
+			};
+			ethernet-phy@2 {
+				compatible = "marvell,mv88e1111";
+				block-index = <2>;
+				reg = <6>;
+			};
+		};
+
+		ethernet@2000 {
+			reg = <2000 2000>;
+			eth0 {
+				device_type = "network";
+				compatible = "marvell,mv64x60-eth";
+				block-index = <0>;
+				interrupts = <20>;
+				interrupt-parent = <&/mv64x60/pic>;
+				phy = <&/mv64x60/mdio/ethernet-phy@0>;
+				speed = <3e8>; 
+				duplex = <1>; 
+				tx_queue_size = <320>;
+				rx_queue_size = <190>;
+				local-mac-address = [ 00 00 00 00 00 00 ];
+			};
+			eth1 {
+				device_type = "network";
+				compatible = "marvell,mv64x60-eth";
+				block-index = <1>;
+				interrupts = <21>;
+				interrupt-parent = <&/mv64x60/pic>;
+				phy = <&/mv64x60/mdio/ethernet-phy@1>;
+				speed = <3e8>; 
+				duplex = <1>; 
+				tx_queue_size = <320>;
+				rx_queue_size = <190>;
+				local-mac-address = [ 00 00 00 00 00 00 ];
+			};
+			eth2 {
+				device_type = "network";
+				compatible = "marvell,mv64x60-eth";
+				block-index = <2>;
+				interrupts = <22>;
+				interrupt-parent = <&/mv64x60/pic>;
+				phy = <&/mv64x60/mdio/ethernet-phy@2>;
+				speed = <3e8>; 
+				duplex = <1>; 
+				tx_queue_size = <320>;
+				rx_queue_size = <190>;
+				local-mac-address = [ 00 00 00 00 00 00 ];
+			};
+		};
+
+		sdma@4000 {
+			compatible = "marvell,mv64x60-sdma";
+			reg = <4000 c18>;
+			virtual-reg = <f8104000>;
+			interrupt-base = <0>;
+			interrupts = <24>;
+			interrupt-parent = <&/mv64x60/pic>;
+		};
+
+		sdma@6000 {
+			compatible = "marvell,mv64x60-sdma";
+			reg = <6000 c18>;
+			virtual-reg = <f8106000>;
+			interrupt-base = <0>;
+			interrupts = <26>;
+			interrupt-parent = <&/mv64x60/pic>;
+		};
+
+		brg@b200 {
+			compatible = "marvell,mv64x60-brg";
+			reg = <b200 8>;
+			clock-src = <8>;
+			clock-frequency = <7ed6b40>;
+			current-speed = <2580>;
+			bcr = <0>;
+		};
+
+		brg@b208 {
+			compatible = "marvell,mv64x60-brg";
+			reg = <b208 8>;
+			clock-src = <8>;
+			clock-frequency = <7ed6b40>;
+			current-speed = <2580>;
+			bcr = <0>;
+		};
+
+		cunit@f200 {
+			reg = <f200 200>;
+		};
+
+		mpscrouting@b400 {
+			reg = <b400 c>;
+		};
+
+		mpscintr@b800 {
+			reg = <b800 100>;
+			virtual-reg = <f810b800>;
+		};
+
+		mpsc@8000 {
+			device_type = "serial";
+			compatible = "marvell,mpsc";
+			reg = <8000 38>;
+			virtual-reg = <f8108000>;
+			sdma = <&/mv64x60/sdma@4000>;
+			brg = <&/mv64x60/brg@b200>;
+			cunit = <&/mv64x60/cunit@f200>;
+			mpscrouting = <&/mv64x60/mpscrouting@b400>;
+			mpscintr = <&/mv64x60/mpscintr@b800>;
+			block-index = <0>;
+			max_idle = <28>;
+			chr_1 = <0>;
+			chr_2 = <0>;
+			chr_10 = <3>;
+			mpcr = <0>;
+			interrupts = <28>;
+			interrupt-parent = <&/mv64x60/pic>;
+		};
+
+		mpsc@9000 {
+			device_type = "serial";
+			compatible = "marvell,mpsc";
+			reg = <9000 38>;
+			virtual-reg = <f8109000>;
+			sdma = <&/mv64x60/sdma@6000>;
+			brg = <&/mv64x60/brg@b208>;
+			cunit = <&/mv64x60/cunit@f200>;
+			mpscrouting = <&/mv64x60/mpscrouting@b400>;
+			mpscintr = <&/mv64x60/mpscintr@b800>;
+			block-index = <1>;
+			max_idle = <28>;
+			chr_1 = <0>;
+			chr_2 = <0>;
+			chr_10 = <3>;
+			mpcr = <0>;
+			interrupts = <29>; 
+			interrupt-parent = <&/mv64x60/pic>;
+		};
+
+		wdt@b410 {			/* watchdog timer */
+			compatible = "marvell,mv64x60-wdt";
+			reg = <b410 8>;
+			timeout = <a>;		/* wdt timeout in seconds */
+		};
+
+		i2c@c000 {
+			compatible = "marvell,mv64x60-i2c";
+			reg = <c000 20>;
+			virtual-reg = <f810c000>;
+			freq_m = <8>;
+			freq_n = <3>;
+			timeout = <3e8>;		/* 1000 = 1 second */
+			retries = <1>;
+			interrupts = <25>;
+			interrupt-parent = <&/mv64x60/pic>;
+		};
+
+		pic {
+			#interrupt-cells = <1>;
+			#address-cells = <0>;
+			compatible = "marvell,mv64x60-pic";
+			reg = <0000 88>;
+			interrupt-controller;
+		};
+
+		mpp@f000 {
+			compatible = "marvell,mv64x60-mpp";
+			reg = <f000 10>;
+		};
+
+		gpp@f100 {
+			compatible = "marvell,mv64x60-gpp";
+			reg = <f100 20>;
+		};
+
+		pci@90000000 {
+			#address-cells = <3>;
+			#size-cells = <2>;
+			#interrupt-cells = <1>;
+			device_type = "pci";
+			compatible = "marvell,mv64x60-pci";
+			reg = <0c78 8>;
+			ranges = <01000000 0        0 c1000000 0 01000000
+				  02000000 0 90000000 90000000 0 30000000>;
+			bus-range = <0 ff>;
+			clock-frequency = <3EF1480>;
+			interrupt-pci-iack = <0c34>;
+			interrupt-parent = <&/mv64x60/pic>;
+			interrupt-map-mask = <f800 0 0 7>;
+			interrupt-map = <
+				/* IDSEL 0x1 */
+				0800 0 0 1 &/mv64x60/pic 5a
+				0800 0 0 2 &/mv64x60/pic 5b
+				0800 0 0 3 &/mv64x60/pic 5e
+				0800 0 0 4 &/mv64x60/pic 5f
+
+				/* IDSEL 0x2 */
+				1000 0 0 1 &/mv64x60/pic 5b
+				1000 0 0 2 &/mv64x60/pic 5e
+				1000 0 0 3 &/mv64x60/pic 5f
+				1000 0 0 4 &/mv64x60/pic 5a
+
+				/* IDSEL 0x3 */
+				1800 0 0 1 &/mv64x60/pic 5e
+				1800 0 0 2 &/mv64x60/pic 5f
+				1800 0 0 3 &/mv64x60/pic 5a
+				1800 0 0 4 &/mv64x60/pic 5b
+
+				/* IDSEL 0x4 */
+				2000 0 0 1 &/mv64x60/pic 5f
+				2000 0 0 2 &/mv64x60/pic 5a
+				2000 0 0 3 &/mv64x60/pic 5b
+				2000 0 0 4 &/mv64x60/pic 5e
+
+				/* IDSEL 0x6 */
+				3000 0 0 1 &/mv64x60/pic 5b
+				3000 0 0 2 &/mv64x60/pic 5e
+				3000 0 0 3 &/mv64x60/pic 5f
+				3000 0 0 4 &/mv64x60/pic 5a
+			>;
+		};
+
+		cpu-error@0070 {
+			compatible = "marvell,mv64x60-cpu-error";
+			reg = <0070 10 0128 28>;
+			interrupts = <03>;
+			interrupt-parent = <&/mv64x60/pic>;
+		};
+
+		sram-ctrl@0380 {
+			compatible = "marvell,mv64x60-sram-ctrl";
+			reg = <0380 80>;
+			interrupts = <0d>;
+			interrupt-parent = <&/mv64x60/pic>;
+		};
+
+		pci-error@1d40 {
+			compatible = "marvell,mv64x60-pci-error";
+			reg = <1d40 40 0c28 4>;
+			interrupts = <0c>;
+			interrupt-parent = <&/mv64x60/pic>;
+		};
+
+		mem-ctrl@1400 {
+			compatible = "marvell,mv64x60-mem-ctrl";
+			reg = <1400 60>;
+			interrupts = <11>;
+			interrupt-parent = <&/mv64x60/pic>;
+		};
+	};
+
+	chosen {
+		bootargs = "ip=on";
+		linux,stdout-path = "/mv64x60@f8100000/mpsc@8000";
+	};
+};

Re: [PATCH 1/5] PowerPC 74xx: Katana Qp device tree

[Vitaly Bordug]

On Fri, 16 Nov 2007 19:12:53 +0300
Andrei Dolnikov wrote:

> Device tree source file for the Emerson Katana Qp board
> 
> Signed-off-by: Andrei Dolnikov <adolnikov@ru.mvisa.com>
> 
> ---
>  arch/powerpc/boot/dts/katanaqp.dts |  357
> +++++++++++++++++++++++++++++++++++++ 1 files changed, 357
> insertions(+)
> 
> diff --git a/arch/powerpc/boot/dts/katanaqp.dts
> b/arch/powerpc/boot/dts/katanaqp.dts new file mode 100644
> index 0000000..9273c4e
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/katanaqp.dts
> @@ -0,0 +1,357 @@
> +/* Device Tree Source for Emerson Katana Qp
> + *
> + * Authors: Vladislav Buzov <vbuzov@ru.mvista.com>
> + *	    Andrei Dolnikov <adolnikov@ru.mvista.com>
> + * 
> + * Based on prpmc8200.dts by Mark A. Greer <mgreer@mvista.com>
> + *
> + * 2007 (c) MontaVista, Software, Inc.  This file is licensed under
> + * the terms of the GNU General Public License version 2.  This
> program
> + * is licensed "as is" without any warranty of any kind, whether
> express
> + * or implied.
> + *
> + */
> +
> +/ {
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	model = "Katana-Qp"; /* Default */
> +	compatible = "emerson,Katana-Qp";
> +	coherency-off;
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		PowerPC,7448@0 {
> +			device_type = "cpu";
> +			reg = <0>;
> +			clock-frequency = <0>;		/*
> From U-boot */
> +			bus-frequency = <0>;		/* From
> U-boot */
> +			timebase-frequency = <0>;	/* From
> U-boot */
> +			i-cache-line-size = <20>;
> +			d-cache-line-size = <20>;
> +			i-cache-size = <8000>;
> +			d-cache-size = <8000>;
> +		};
> +	};
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <00000000 20000000>;	/* Default (512MB)
> */
> +	};
> +

shouldn't this come from the firmware if possible?
> +	mv64x60@f8100000 { /* Marvell Discovery */
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		model = "mv64460";			/* Default
> */
> +		compatible = "marvell,mv64x60";
> +		clock-frequency = <7f28155>;		/*
> 133.333333 MHz */
This should be updated somewhere in fw or bootwrapper.. Or is it hardcoded
value that is not going to change?

> +		reg = <f8100000 00010000>;
> +		virtual-reg = <f8100000>;
> +		ranges = <c1000000 c1000000 01000000	/* PCI 1
> I/O Space */
> +			  90000000 90000000 30000000	/* PCI 1
> MEM Space */
> +			  e8000000 e8000000 04000000	/* User
> FLASH: Up to 64Mb */
> +			  00000000 f8100000 00010000	/*
> Bridge's regs */
> +			  f8500000 f8500000 00040000>;	/*
> Integrated SRAM */ +
> +		flash@e8000000 {
> +			compatible = "cfi-flash";
> +			reg = <e8000000 1000000>; /* Default (16MB)
> */
> +			probe-type = "CFI";
> +			bank-width = <4>;
> +			
> +			partition@0 {
> +				label = "Primary Monitor";
> +				reg = <0 100000>; /* 1Mb */
> +				read-only;
> +			};
> +
> +			partition@100000 {
> +				label = "Primary Kernel";
> +				reg = <100000 200000>; /* 2 Mb */
> +			};
> +
> +			partition@300000 {
> +				label = "Primary FS";
> +				reg = <300000 d00000>; /* 13 Mb */
> +			};
> +
> +		};
> +
> +		cpld@f8200000 {
> +			compatible = "altera,maxii";
> +			reg = <f8200000 40000>;
> +			virtual-reg = <f8200000>;
> +		};
> +
> +		mdio {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			compatible = "marvell,mv64x60-mdio";
> +			ethernet-phy@0 {
> +				block-index = <0>;
> +				compatible = "marvell,mv88e1111";
> +				reg = <a>;
> +			};
> +			ethernet-phy@1 {
> +				compatible = "marvell,mv88e1111";
> +				block-index = <1>;
> +				reg = <d>;
> +			};
> +			ethernet-phy@2 {
> +				compatible = "marvell,mv88e1111";
> +				block-index = <2>;
> +				reg = <6>;
> +			};
> +		};
> +
> +		ethernet@2000 {
> +			reg = <2000 2000>;
> +			eth0 {
> +				device_type = "network";
> +				compatible = "marvell,mv64x60-eth";
> +				block-index = <0>;
> +				interrupts = <20>;
> +				interrupt-parent = <&/mv64x60/pic>;
> +				phy =
> <&/mv64x60/mdio/ethernet-phy@0>;
> +				speed = <3e8>; 
> +				duplex = <1>; 
> +				tx_queue_size = <320>;
> +				rx_queue_size = <190>;
> +				local-mac-address = [ 00 00 00 00 00
> 00 ];
> +			};
> +			eth1 {
> +				device_type = "network";
> +				compatible = "marvell,mv64x60-eth";
> +				block-index = <1>;
> +				interrupts = <21>;
> +				interrupt-parent = <&/mv64x60/pic>;
> +				phy =
> <&/mv64x60/mdio/ethernet-phy@1>;
> +				speed = <3e8>; 
> +				duplex = <1>; 
> +				tx_queue_size = <320>;
> +				rx_queue_size = <190>;
> +				local-mac-address = [ 00 00 00 00 00
> 00 ];
here and in other places: you need to add a note that stuff is being rewritten/updated by fw and/or bootwrapper.
> +			};
> +			eth2 {
> +				device_type = "network";
> +				compatible = "marvell,mv64x60-eth";
> +				block-index = <2>;
> +				interrupts = <22>;
> +				interrupt-parent = <&/mv64x60/pic>;
> +				phy =
> <&/mv64x60/mdio/ethernet-phy@2>;
> +				speed = <3e8>; 
> +				duplex = <1>; 
> +				tx_queue_size = <320>;
> +				rx_queue_size = <190>;
> +				local-mac-address = [ 00 00 00 00 00
> 00 ];
> +			};
> +		};
> +
> +		sdma@4000 {
> +			compatible = "marvell,mv64x60-sdma";
> +			reg = <4000 c18>;
> +			virtual-reg = <f8104000>;
> +			interrupt-base = <0>;
> +			interrupts = <24>;
> +			interrupt-parent = <&/mv64x60/pic>;
> +		};
> +
> +		sdma@6000 {
> +			compatible = "marvell,mv64x60-sdma";
> +			reg = <6000 c18>;
> +			virtual-reg = <f8106000>;
> +			interrupt-base = <0>;
> +			interrupts = <26>;
> +			interrupt-parent = <&/mv64x60/pic>;
> +		};
> +
> +		brg@b200 {
> +			compatible = "marvell,mv64x60-brg";
> +			reg = <b200 8>;
> +			clock-src = <8>;
> +			clock-frequency = <7ed6b40>;
> +			current-speed = <2580>;
> +			bcr = <0>;
> +		};
> +
> +		brg@b208 {
> +			compatible = "marvell,mv64x60-brg";
> +			reg = <b208 8>;
> +			clock-src = <8>;
> +			clock-frequency = <7ed6b40>;
> +			current-speed = <2580>;
> +			bcr = <0>;
> +		};
> +
> +		cunit@f200 {
> +			reg = <f200 200>;
> +		};
> +
> +		mpscrouting@b400 {
> +			reg = <b400 c>;
> +		};
> +
> +		mpscintr@b800 {
> +			reg = <b800 100>;
> +			virtual-reg = <f810b800>;
> +		};
> +
> +		mpsc@8000 {
> +			device_type = "serial";
> +			compatible = "marvell,mpsc";
> +			reg = <8000 38>;
> +			virtual-reg = <f8108000>;
> +			sdma = <&/mv64x60/sdma@4000>;
> +			brg = <&/mv64x60/brg@b200>;
> +			cunit = <&/mv64x60/cunit@f200>;
> +			mpscrouting = <&/mv64x60/mpscrouting@b400>;
> +			mpscintr = <&/mv64x60/mpscintr@b800>;
> +			block-index = <0>;
> +			max_idle = <28>;
> +			chr_1 = <0>;
> +			chr_2 = <0>;
> +			chr_10 = <3>;
> +			mpcr = <0>;
> +			interrupts = <28>;
> +			interrupt-parent = <&/mv64x60/pic>;
> +		};
> +
> +		mpsc@9000 {
> +			device_type = "serial";
> +			compatible = "marvell,mpsc";
> +			reg = <9000 38>;
> +			virtual-reg = <f8109000>;
> +			sdma = <&/mv64x60/sdma@6000>;
> +			brg = <&/mv64x60/brg@b208>;
> +			cunit = <&/mv64x60/cunit@f200>;
> +			mpscrouting = <&/mv64x60/mpscrouting@b400>;
> +			mpscintr = <&/mv64x60/mpscintr@b800>;
> +			block-index = <1>;
> +			max_idle = <28>;
> +			chr_1 = <0>;
> +			chr_2 = <0>;
> +			chr_10 = <3>;
> +			mpcr = <0>;
> +			interrupts = <29>; 
> +			interrupt-parent = <&/mv64x60/pic>;
> +		};
> +
> +		wdt@b410 {			/* watchdog timer
> */
> +			compatible = "marvell,mv64x60-wdt";
> +			reg = <b410 8>;
> +			timeout = <a>;		/* wdt timeout
> in seconds */
> +		};
> +
> +		i2c@c000 {
> +			compatible = "marvell,mv64x60-i2c";
> +			reg = <c000 20>;
> +			virtual-reg = <f810c000>;
> +			freq_m = <8>;
> +			freq_n = <3>;
> +			timeout = <3e8>;		/* 1000 = 1
> second */
> +			retries = <1>;
> +			interrupts = <25>;
> +			interrupt-parent = <&/mv64x60/pic>;
> +		};
> +
> +		pic {
> +			#interrupt-cells = <1>;
> +			#address-cells = <0>;
> +			compatible = "marvell,mv64x60-pic";
> +			reg = <0000 88>;
> +			interrupt-controller;
> +		};
> +
> +		mpp@f000 {
> +			compatible = "marvell,mv64x60-mpp";
> +			reg = <f000 10>;
> +		};
> +
> +		gpp@f100 {
> +			compatible = "marvell,mv64x60-gpp";
> +			reg = <f100 20>;
> +		};
> +
> +		pci@90000000 {
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +			#interrupt-cells = <1>;
> +			device_type = "pci";
> +			compatible = "marvell,mv64x60-pci";
> +			reg = <0c78 8>;
> +			ranges = <01000000 0        0 c1000000 0
> 01000000
> +				  02000000 0 90000000 90000000 0
> 30000000>;
> +			bus-range = <0 ff>;
> +			clock-frequency = <3EF1480>;
> +			interrupt-pci-iack = <0c34>;
> +			interrupt-parent = <&/mv64x60/pic>;
> +			interrupt-map-mask = <f800 0 0 7>;
> +			interrupt-map = <
> +				/* IDSEL 0x1 */
> +				0800 0 0 1 &/mv64x60/pic 5a
> +				0800 0 0 2 &/mv64x60/pic 5b
> +				0800 0 0 3 &/mv64x60/pic 5e
> +				0800 0 0 4 &/mv64x60/pic 5f
> +
> +				/* IDSEL 0x2 */
> +				1000 0 0 1 &/mv64x60/pic 5b
> +				1000 0 0 2 &/mv64x60/pic 5e
> +				1000 0 0 3 &/mv64x60/pic 5f
> +				1000 0 0 4 &/mv64x60/pic 5a
> +
> +				/* IDSEL 0x3 */
> +				1800 0 0 1 &/mv64x60/pic 5e
> +				1800 0 0 2 &/mv64x60/pic 5f
> +				1800 0 0 3 &/mv64x60/pic 5a
> +				1800 0 0 4 &/mv64x60/pic 5b
> +
> +				/* IDSEL 0x4 */
> +				2000 0 0 1 &/mv64x60/pic 5f
> +				2000 0 0 2 &/mv64x60/pic 5a
> +				2000 0 0 3 &/mv64x60/pic 5b
> +				2000 0 0 4 &/mv64x60/pic 5e
> +
> +				/* IDSEL 0x6 */
> +				3000 0 0 1 &/mv64x60/pic 5b
> +				3000 0 0 2 &/mv64x60/pic 5e
> +				3000 0 0 3 &/mv64x60/pic 5f
> +				3000 0 0 4 &/mv64x60/pic 5a
> +			>;
> +		};
> +
> +		cpu-error@0070 {
> +			compatible = "marvell,mv64x60-cpu-error";
> +			reg = <0070 10 0128 28>;
> +			interrupts = <03>;
> +			interrupt-parent = <&/mv64x60/pic>;
> +		};
> +
> +		sram-ctrl@0380 {
> +			compatible = "marvell,mv64x60-sram-ctrl";
> +			reg = <0380 80>;
> +			interrupts = <0d>;
> +			interrupt-parent = <&/mv64x60/pic>;
> +		};
> +
> +		pci-error@1d40 {
> +			compatible = "marvell,mv64x60-pci-error";
> +			reg = <1d40 40 0c28 4>;
> +			interrupts = <0c>;
> +			interrupt-parent = <&/mv64x60/pic>;
> +		};
> +
> +		mem-ctrl@1400 {
> +			compatible = "marvell,mv64x60-mem-ctrl";
> +			reg = <1400 60>;
> +			interrupts = <11>;
> +			interrupt-parent = <&/mv64x60/pic>;
> +		};
> +	};
> +
> +	chosen {
> +		bootargs = "ip=on";
> +		linux,stdout-path = "/mv64x60@f8100000/mpsc@8000";
> +	};
Not sure it is required. At least if u-boot would have OF support, it'll rewrite chosen...
> +};
> 
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev


-- 
Sincerely, Vitaly

[PATCH 0/5] PowerPC 74xx: Add Emerson Katana Qp support

[Andrei Dolnikov]

Hello folks,

The following patch sequence is Emerson KatanaQp board support reworked after initial review/discussion.
The patches are incremental to minor mv64x60 code fixups sent by
Mark A. Greer on 11/08/07.

Let me know if you think that some updates/changes needed.


As for Vitaly's and Arnd's questions:

Vitaly Bordug wrote:
>> +		clock-frequency = <7f28155>;		/*
>> 133.333333 MHz */
>This should be updated somewhere in fw or bootwrapper.. Or is it hardcoded
>value that is not going to change?
Yep, it is :)

About cfi-flash: I leave this code as is, according to Benjamin comment.

Thanks,
Andrei.

[PATCH 1/5] PowerPC 74xx: Katana Qp device tree

[Andrei Dolnikov]

Device tree source file for the Emerson Katana Qp board

Signed-off-by: Andrei Dolnikov <adolnikov@ru.mvisa.com>

---
 katanaqp.dts |  360 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 360 insertions(+)

diff --git a/arch/powerpc/boot/dts/katanaqp.dts b/arch/powerpc/boot/dts/katanaqp.dts
new file mode 100644
index 0000000..98257a2
--- /dev/null
+++ b/arch/powerpc/boot/dts/katanaqp.dts
@@ -0,0 +1,360 @@
+/* Device Tree Source for Emerson Katana Qp
+ *
+ * Authors: Vladislav Buzov <vbuzov@ru.mvista.com>
+ *	    Andrei Dolnikov <adolnikov@ru.mvista.com>
+ * 
+ * Based on prpmc8200.dts by Mark A. Greer <mgreer@mvista.com>
+ *
+ * 2007 (c) MontaVista, Software, Inc.  This file is licensed under
+ * the terms of the GNU General Public License version 2.  This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ */
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	model = "Katana-Qp"; /* Default */
+	compatible = "emerson,Katana-Qp";
+	coherency-off;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,7448@0 {
+			device_type = "cpu";
+			reg = <0>;
+			clock-frequency = <0>;		/* From U-boot */
+			bus-frequency = <0>;		/* From U-boot */
+			timebase-frequency = <0>;	/* From U-boot */
+			i-cache-line-size = <20>;
+			d-cache-line-size = <20>;
+			i-cache-size = <8000>;
+			d-cache-size = <8000>;
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <00000000 00000000>;	/* Filled in by bootwrapper */
+	};
+
+	mv64x60@f8100000 { /* Marvell Discovery */
+		#address-cells = <1>;
+		#size-cells = <1>;
+		model = "mv64460";			/* Default */
+		compatible = "marvell,mv64x60";
+		clock-frequency = <7f28155>;		/* 133.333333 MHz */
+		reg = <f8100000 00010000>;
+		virtual-reg = <f8100000>;
+		ranges = <c1000000 c1000000 01000000	/* PCI 1 I/O Space */
+			  90000000 90000000 30000000	/* PCI 1 MEM Space */
+			  e8000000 e8000000 04000000	/* User FLASH: Up to 64Mb */
+			  00000000 f8100000 00010000	/* Bridge's regs */
+			  f8500000 f8500000 00040000>;	/* Integrated SRAM */
+
+		flash@e8000000 {
+			compatible = "cfi-flash";
+			reg = <e8000000 1000000>; /* Default (16MB) */
+			probe-type = "CFI";
+			bank-width = <4>;
+			
+			partition@0 {
+				label = "Primary Monitor";
+				reg = <0 100000>; /* 1Mb */
+				read-only;
+			};
+
+			partition@100000 {
+				label = "Primary Kernel";
+				reg = <100000 200000>; /* 2 Mb */
+			};
+
+			partition@300000 {
+				label = "Primary FS";
+				reg = <300000 d00000>; /* 13 Mb */
+			};
+
+		};
+
+		mdio {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "marvell,mv64x60-mdio";
+			ethernet-phy@0 {
+				block-index = <0>;
+				compatible = "marvell,mv88e1111";
+				reg = <a>;
+			};
+			ethernet-phy@1 {
+				compatible = "marvell,mv88e1111";
+				block-index = <1>;
+				reg = <d>;
+			};
+			ethernet-phy@2 {
+				compatible = "marvell,mv88e1111";
+				block-index = <2>;
+				reg = <6>;
+			};
+		};
+
+		ethernet@2000 {
+			reg = <2000 2000>;
+			eth0 {
+				device_type = "network";
+				compatible = "marvell,mv64x60-eth";
+				block-index = <0>;
+				interrupts = <20>;
+				interrupt-parent = <&/mv64x60/pic>;
+				phy = <&/mv64x60/mdio/ethernet-phy@0>;
+				speed = <3e8>; 
+				duplex = <1>; 
+				tx_queue_size = <320>;
+				rx_queue_size = <190>;
+				local-mac-address = [ 00 00 00 00 00 00 ];
+				/* Mac address filled in by bootwrapper */
+			};
+			eth1 {
+				device_type = "network";
+				compatible = "marvell,mv64x60-eth";
+				block-index = <1>;
+				interrupts = <21>;
+				interrupt-parent = <&/mv64x60/pic>;
+				phy = <&/mv64x60/mdio/ethernet-phy@1>;
+				speed = <3e8>; 
+				duplex = <1>; 
+				tx_queue_size = <320>;
+				rx_queue_size = <190>;
+				local-mac-address = [ 00 00 00 00 00 00 ];
+				/* Mac address filled in by bootwrapper */
+			};
+			eth2 {
+				device_type = "network";
+				compatible = "marvell,mv64x60-eth";
+				block-index = <2>;
+				interrupts = <22>;
+				interrupt-parent = <&/mv64x60/pic>;
+				phy = <&/mv64x60/mdio/ethernet-phy@2>;
+				speed = <3e8>; 
+				duplex = <1>; 
+				tx_queue_size = <320>;
+				rx_queue_size = <190>;
+				local-mac-address = [ 00 00 00 00 00 00 ];
+				/* Mac address filled in by bootwrapper */
+			};
+		};
+
+		sdma@4000 {
+			compatible = "marvell,mv64x60-sdma";
+			reg = <4000 c18>;
+			virtual-reg = <f8104000>;
+			interrupt-base = <0>;
+			interrupts = <24>;
+			interrupt-parent = <&/mv64x60/pic>;
+		};
+
+		sdma@6000 {
+			compatible = "marvell,mv64x60-sdma";
+			reg = <6000 c18>;
+			virtual-reg = <f8106000>;
+			interrupt-base = <0>;
+			interrupts = <26>;
+			interrupt-parent = <&/mv64x60/pic>;
+		};
+
+		brg@b200 {
+			compatible = "marvell,mv64x60-brg";
+			reg = <b200 8>;
+			clock-src = <8>;
+			clock-frequency = <7ed6b40>;
+			current-speed = <2580>;
+			bcr = <0>;
+		};
+
+		brg@b208 {
+			compatible = "marvell,mv64x60-brg";
+			reg = <b208 8>;
+			clock-src = <8>;
+			clock-frequency = <7ed6b40>;
+			current-speed = <2580>;
+			bcr = <0>;
+		};
+
+		cunit@f200 {
+			reg = <f200 200>;
+		};
+
+		mpscrouting@b400 {
+			reg = <b400 c>;
+		};
+
+		mpscintr@b800 {
+			reg = <b800 100>;
+			virtual-reg = <f810b800>;
+		};
+
+		mpsc@8000 {
+			device_type = "serial";
+			compatible = "marvell,mpsc";
+			reg = <8000 38>;
+			virtual-reg = <f8108000>;
+			sdma = <&/mv64x60/sdma@4000>;
+			brg = <&/mv64x60/brg@b200>;
+			cunit = <&/mv64x60/cunit@f200>;
+			mpscrouting = <&/mv64x60/mpscrouting@b400>;
+			mpscintr = <&/mv64x60/mpscintr@b800>;
+			block-index = <0>;
+			max_idle = <28>;
+			chr_1 = <0>;
+			chr_2 = <0>;
+			chr_10 = <3>;
+			mpcr = <0>;
+			interrupts = <28>;
+			interrupt-parent = <&/mv64x60/pic>;
+		};
+
+		mpsc@9000 {
+			device_type = "serial";
+			compatible = "marvell,mpsc";
+			reg = <9000 38>;
+			virtual-reg = <f8109000>;
+			sdma = <&/mv64x60/sdma@6000>;
+			brg = <&/mv64x60/brg@b208>;
+			cunit = <&/mv64x60/cunit@f200>;
+			mpscrouting = <&/mv64x60/mpscrouting@b400>;
+			mpscintr = <&/mv64x60/mpscintr@b800>;
+			block-index = <1>;
+			max_idle = <28>;
+			chr_1 = <0>;
+			chr_2 = <0>;
+			chr_10 = <3>;
+			mpcr = <0>;
+			interrupts = <29>; 
+			interrupt-parent = <&/mv64x60/pic>;
+		};
+
+		wdt@b410 {			/* watchdog timer */
+			compatible = "marvell,mv64x60-wdt";
+			reg = <b410 8>;
+			timeout = <a>;		/* wdt timeout in seconds */
+		};
+
+		i2c@c000 {
+			compatible = "marvell,mv64x60-i2c";
+			reg = <c000 20>;
+			virtual-reg = <f810c000>;
+			freq_m = <8>;
+			freq_n = <3>;
+			timeout = <3e8>;		/* 1000 = 1 second */
+			retries = <1>;
+			interrupts = <25>;
+			interrupt-parent = <&/mv64x60/pic>;
+		};
+
+		pic {
+			#interrupt-cells = <1>;
+			#address-cells = <0>;
+			compatible = "marvell,mv64x60-pic";
+			reg = <0000 88>;
+			interrupt-controller;
+		};
+
+		mpp@f000 {
+			compatible = "marvell,mv64x60-mpp";
+			reg = <f000 10>;
+		};
+
+		gpp@f100 {
+			compatible = "marvell,mv64x60-gpp";
+			reg = <f100 20>;
+		};
+
+		pci@90000000 {
+			#address-cells = <3>;
+			#size-cells = <2>;
+			#interrupt-cells = <1>;
+			device_type = "pci";
+			compatible = "marvell,mv64x60-pci";
+			reg = <0c78 8>;
+			ranges = <01000000 0        0 c1000000 0 01000000
+				  02000000 0 90000000 90000000 0 30000000>;
+			bus-range = <0 ff>;
+			clock-frequency = <3EF1480>;
+			interrupt-pci-iack = <0c34>;
+			interrupt-parent = <&/mv64x60/pic>;
+			interrupt-map-mask = <f800 0 0 7>;
+			interrupt-map = <
+				/* IDSEL 0x1 */
+				0800 0 0 1 &/mv64x60/pic 5a
+				0800 0 0 2 &/mv64x60/pic 5b
+				0800 0 0 3 &/mv64x60/pic 5e
+				0800 0 0 4 &/mv64x60/pic 5f
+
+				/* IDSEL 0x2 */
+				1000 0 0 1 &/mv64x60/pic 5b
+				1000 0 0 2 &/mv64x60/pic 5e
+				1000 0 0 3 &/mv64x60/pic 5f
+				1000 0 0 4 &/mv64x60/pic 5a
+
+				/* IDSEL 0x3 */
+				1800 0 0 1 &/mv64x60/pic 5e
+				1800 0 0 2 &/mv64x60/pic 5f
+				1800 0 0 3 &/mv64x60/pic 5a
+				1800 0 0 4 &/mv64x60/pic 5b
+
+				/* IDSEL 0x4 */
+				2000 0 0 1 &/mv64x60/pic 5f
+				2000 0 0 2 &/mv64x60/pic 5a
+				2000 0 0 3 &/mv64x60/pic 5b
+				2000 0 0 4 &/mv64x60/pic 5e
+
+				/* IDSEL 0x6 */
+				3000 0 0 1 &/mv64x60/pic 5b
+				3000 0 0 2 &/mv64x60/pic 5e
+				3000 0 0 3 &/mv64x60/pic 5f
+				3000 0 0 4 &/mv64x60/pic 5a
+			>;
+		};
+
+		cpu-error@0070 {
+			compatible = "marvell,mv64x60-cpu-error";
+			reg = <0070 10 0128 28>;
+			interrupts = <03>;
+			interrupt-parent = <&/mv64x60/pic>;
+		};
+
+		sram-ctrl@0380 {
+			compatible = "marvell,mv64x60-sram-ctrl";
+			reg = <0380 80>;
+			interrupts = <0d>;
+			interrupt-parent = <&/mv64x60/pic>;
+		};
+
+		pci-error@1d40 {
+			compatible = "marvell,mv64x60-pci-error";
+			reg = <1d40 40 0c28 4>;
+			interrupts = <0c>;
+			interrupt-parent = <&/mv64x60/pic>;
+		};
+
+		mem-ctrl@1400 {
+			compatible = "marvell,mv64x60-mem-ctrl";
+			reg = <1400 60>;
+			interrupts = <11>;
+			interrupt-parent = <&/mv64x60/pic>;
+		};
+	};
+
+	cpld@f8200000 {
+		compatible = "altera,maxii";
+		reg = <f8200000 40000>;
+		virtual-reg = <f8200000>;
+	};
+
+	chosen {
+		bootargs = "ip=on";
+		linux,stdout-path = "/mv64x60@f8100000/mpsc@8000";
+	};
+};

[PATCH 2/5] PowerPC 74xx: Minor updates to MV64x60 boot code

[Andrei Dolnikov]

This patch adds new functionality to MV64x60 boot code. The changes are required
to access DevCS windows registers and set PCI bus and devfn numbers for MV644x60
PCI/PCI-X interfaces.

Signed-off-by: Andrei Dolnikov <adolnikov@ru.mvista.com>

---
 mv64x60.c |   74 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 mv64x60.h |   10 ++++++++
 2 files changed, 84 insertions(+)

diff --git a/arch/powerpc/boot/mv64x60.c b/arch/powerpc/boot/mv64x60.c
index d207a0b..787a124 100644
--- a/arch/powerpc/boot/mv64x60.c
+++ b/arch/powerpc/boot/mv64x60.c
@@ -32,6 +32,16 @@
 #define MV64x60_CPU2MEM_3_BASE			0x0218
 #define MV64x60_CPU2MEM_3_SIZE			0x0220
 
+#define MV64x60_DEV2MEM_WINDOWS			4
+#define MV64x60_DEV2MEM_0_BASE			0x0028
+#define MV64x60_DEV2MEM_0_SIZE			0x0030
+#define MV64x60_DEV2MEM_1_BASE			0x0228
+#define MV64x60_DEV2MEM_1_SIZE			0x0230
+#define MV64x60_DEV2MEM_2_BASE			0x0248
+#define MV64x60_DEV2MEM_2_SIZE			0x0250
+#define MV64x60_DEV2MEM_3_BASE			0x0038
+#define MV64x60_DEV2MEM_3_SIZE			0x0040
+
 #define MV64x60_ENET2MEM_BAR_ENABLE		0x2290
 #define MV64x60_ENET2MEM_0_BASE			0x2200
 #define MV64x60_ENET2MEM_0_SIZE			0x2204
@@ -219,6 +229,25 @@ static struct mv64x60_mem_win mv64x60_cpu2mem[MV64x60_CPU2MEM_WINDOWS] = {
 	},
 };
 
+static struct mv64x60_mem_win mv64x60_devcs[MV64x60_DEV2MEM_WINDOWS] = {
+	[0] = {
+		.lo	= MV64x60_DEV2MEM_0_BASE,
+		.size	= MV64x60_DEV2MEM_0_SIZE,
+	},
+	[1] = {
+		.lo	= MV64x60_DEV2MEM_1_BASE,
+		.size	= MV64x60_DEV2MEM_1_SIZE,
+	},
+	[2] = {
+		.lo	= MV64x60_DEV2MEM_2_BASE,
+		.size	= MV64x60_DEV2MEM_2_SIZE,
+	},
+	[3] = {
+		.lo	= MV64x60_DEV2MEM_3_BASE,
+		.size	= MV64x60_DEV2MEM_3_SIZE,
+	},
+};
+
 static struct mv64x60_mem_win mv64x60_enet2mem[MV64x60_CPU2MEM_WINDOWS] = {
 	[0] = {
 		.lo	= MV64x60_ENET2MEM_0_BASE,
@@ -567,6 +596,36 @@ void mv64x60_config_cpu2pci_window(u8 *bridge_base, u8 hose, u32 pci_base_hi,
 	out_le32((u32 *)(bridge_base + offset_tbl[hose].size), size);
 }
 
+/* Set PCI bus number for a PCI interface and force its devnum to 0 */
+void mv64x60_set_pci_bus(u8 *bridge_base, u8 hose, u32 bus, u32 devnum)
+{
+	u8 *pci_mode_reg, *p2p_cfg_reg;
+	u32 pci_mode, p2p_cfg;
+	u32 pci_cfg_offset;
+	
+	if (hose == 0) {
+		pci_mode_reg = bridge_base + MV64x60_PCI0_MODE;
+		p2p_cfg_reg = bridge_base + MV64x60_PCI0_P2P_CONF;
+		pci_cfg_offset = 0x64;
+	} else {
+		pci_mode_reg = bridge_base + MV64x60_PCI1_MODE;
+		p2p_cfg_reg = bridge_base + MV64x60_PCI1_P2P_CONF;
+		pci_cfg_offset = 0xe4;
+	}
+
+	pci_mode = in_le32((u32*)pci_mode_reg) & MV64x60_PCI_MODE_MASK;
+	p2p_cfg = in_le32((u32*)p2p_cfg_reg);
+
+	if (pci_mode == MV64x60_PCI_CONVENTIONAL_MODE) {
+		p2p_cfg &= 0xe0000000;
+		p2p_cfg |= (devnum << 24) | (bus << 16) | 0xff;
+		out_le32((u32*)p2p_cfg_reg, p2p_cfg);
+	} else
+		mv64x60_cfg_write(bridge_base, hose, (p2p_cfg >> 16) & 0xff,
+				 PCI_DEVFN((p2p_cfg >> 24) & 0x1f, 0),
+				 pci_cfg_offset, (devnum << 3) | (bus << 8));
+}
+
 /* Read mem ctlr to get the amount of mem in system */
 u32 mv64x60_get_mem_size(u8 *bridge_base)
 {
@@ -586,6 +645,21 @@ u32 mv64x60_get_mem_size(u8 *bridge_base)
 	return mem;
 }
 
+/* Read a size of DEV_CS window */
+u32 mv64x60_get_devcs_size(u8 *bridge_base, u32 devcs)
+{
+	u32 enables, size = 0;
+
+	enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE)) & 0xf0;
+	
+	if (devcs < 4 && !(enables && (0x10 << devcs))) {
+		size = in_le32((u32*)(bridge_base + mv64x60_devcs[devcs].size));
+		size = ((size & 0xffff) + 1) << 16;
+	}
+
+	return size;
+}
+
 /* Get physical address of bridge's registers */
 u8 *mv64x60_get_bridge_pbase(void)
 {
diff --git a/arch/powerpc/boot/mv64x60.h b/arch/powerpc/boot/mv64x60.h
index d0b29a7..a633d2e 100644
--- a/arch/powerpc/boot/mv64x60.h
+++ b/arch/powerpc/boot/mv64x60.h
@@ -12,6 +12,14 @@
 
 #define MV64x60_CPU_BAR_ENABLE			0x0278
 
+#define MV64x60_PCI0_MODE			0x0d00
+#define MV64x60_PCI1_MODE			0x0d80
+#define MV64x60_PCI0_P2P_CONF			0x1d14
+#define MV64x60_PCI1_P2P_CONF			0x1d94
+
+#define MV64x60_PCI_MODE_MASK			0x00000030
+#define MV64x60_PCI_CONVENTIONAL_MODE		0x00000000
+
 #define MV64x60_PCI_ACC_CNTL_ENABLE		(1<<0)
 #define MV64x60_PCI_ACC_CNTL_REQ64		(1<<1)
 #define MV64x60_PCI_ACC_CNTL_SNOOP_NONE		0x00000000
@@ -57,7 +65,9 @@ void mv64x60_config_pci_windows(u8 *bridge_base, u8 *bridge_pbase, u8 hose,
 void mv64x60_config_cpu2pci_window(u8 *bridge_base, u8 hose, u32 pci_base_hi,
 		u32 pci_base_lo, u32 cpu_base, u32 size,
 		struct mv64x60_cpu2pci_win *offset_tbl);
+void mv64x60_set_pci_bus(u8 *bridge_base, u8 hose, u32 bus, u32 devnum);
 u32 mv64x60_get_mem_size(u8 *bridge_base);
+u32 mv64x60_get_devcs_size(u8 *bridge_base, u32 devcs);
 u8 *mv64x60_get_bridge_pbase(void);
 u8 *mv64x60_get_bridge_base(void);
 u8 mv64x60_is_coherent(void);

[PATCH 3/5] PowerPC 74xx: Katana Qp bootwrapper

[Andrei Dolnikov]

Bootwrapper sources for Emerson Katana Qp

Signed-off-by: Andrei Dolnikov <adolnikov@ru.mvista.com>

---
 Makefile          |    3
 cuboot-katanaqp.c |  470 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 472 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index 18e3271..92b8fac 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -56,7 +56,7 @@ src-plat := of.c cuboot-52xx.c cuboot-83xx.c cuboot-85xx.c holly.c \
 		cuboot-ebony.c treeboot-ebony.c prpmc2800.c \
 		ps3-head.S ps3-hvcall.S ps3.c treeboot-bamboo.c cuboot-8xx.c \
 		cuboot-pq2.c cuboot-sequoia.c treeboot-walnut.c cuboot-bamboo.c \
-		fixed-head.S ep88xc.c cuboot-hpc2.c
+		fixed-head.S ep88xc.c cuboot-hpc2.c cuboot-katanaqp.c
 src-boot := $(src-wlib) $(src-plat) empty.c
 
 src-boot := $(addprefix $(obj)/, $(src-boot))
@@ -159,6 +159,7 @@ image-$(CONFIG_EBONY)			+= treeImage.ebony cuImage.ebony
 image-$(CONFIG_BAMBOO)			+= treeImage.bamboo cuImage.bamboo
 image-$(CONFIG_SEQUOIA)			+= cuImage.sequoia
 image-$(CONFIG_WALNUT)			+= treeImage.walnut
+image-$(CONFIG_PPC_KATANAQP)		+= cuImage.katanaqp
 endif
 
 # For 32-bit powermacs, build the COFF and miboot images
diff --git a/arch/powerpc/boot/cuboot-katanaqp.c b/arch/powerpc/boot/cuboot-katanaqp.c
new file mode 100644
index 0000000..19ba901
--- /dev/null
+++ b/arch/powerpc/boot/cuboot-katanaqp.c
@@ -0,0 +1,470 @@
+/*
+ * Emerson Katana Qp platform code.
+ *
+ * Authors: Vladislav Buzov <buzov@ru.mvista.com>
+ *	    Andrei Dolnikov <adolnikov@ru.mvista.com>
+ *
+ * Based on prpmc2800.c by Mark A. Greer <mgreer@mvista.com>
+ *
+ * 2007 (c) MontaVista, Software, Inc.  This file is licensed under
+ * the terms of the GNU General Public License version 2.  This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include <stdarg.h>
+#include <stddef.h>
+#include "cuboot.h"
+#include "ppcboot.h"
+#include "types.h"
+#include "page.h"
+#include "string.h"
+#include "stdio.h"
+#include "io.h"
+#include "ops.h"
+#include "mv64x60.h"
+
+#define Mb	(1024U * 1024U)
+#define Gb	(Mb * 1024U)
+
+#define MHz	(1000U * 1000U)
+#define GHz	(MHz * 1000U)
+
+#define BOARD_MODEL		"Katana-Qp"
+#define BOARD_MODEL_MAX		12	/* max strlen(BOARD_MODEL) + 1 */
+#define BOARD_CFG_MAX		28	/* max strlen(BOARD_CFG) + 1 */
+#define BOARD_MODEL_LEN		(BOARD_MODEL_MAX + BOARD_CFG_MAX)
+
+#define MTD_PART_NODE		"partition"
+#define MTD_PART_NUM		3
+#define MTD_PART_NODE_LEN	20
+#define MTD_PART_MONITOR_SIZE	(1*Mb)
+#define MTD_PART_KERNEL_SIZE	(2*Mb)
+
+/*
+ * CPLD registers definitions
+ */
+#define KATANAQP_CPLD_RCR	0x0004	/* Reset command */
+#define KATANAQP_CPLD_RCR_CPUHR	(1 << 7)
+
+#define KATANAQP_CPLD_JSR	0x0020	/* Jumper settings */
+#define KATANAQP_CPLD_JSR_EBFM	(1 << 6)
+
+#define KATANAQP_CPLD_PSR	0x0030	/* PCI status */
+#define KATANAQP_CPLD_PSR_PMCM	(1 << 1)
+
+#define KATANAQP_CPLD_HCR	0x0044	/* Hardware config */
+
+static bd_t bd;
+
+static u8 *bridge_base;
+static u8 *cpld_base;
+
+typedef enum {
+	KATANAQP_UNKNOWN,
+	KATANAQP_CFG_PRPMC_SINGLE,
+	KATANAQP_CFG_PRPMC_DUAL,
+	KATANAQP_CFG_PT2CC_SINGLE,
+	KATANAQP_CFG_PT5CC_SINGLE,
+	KATANAQP_CFG_MEDIA_DUAL,
+	KATANAQP_CFG_PT2CC_DUAL,
+	KATANAQP_CFG_PT5CC_DUAL,
+	KATANAQP_CFG_PT5CC_CUSTOM,
+	KATANAQP_CFG_MEDIA_SINGLE,
+	KATANAQP_CFG_UNKNOWN,
+} katanaqp_board_model;
+
+static katanaqp_board_model katanaqp_cfg;
+
+struct katanaqp_board_info {
+	char *cfg_name;
+	char eth_phys[3];
+};
+
+struct katanaqp_mtd_part {
+	char *name;
+	u32 size;
+	u32 ro;
+};
+
+static struct katanaqp_board_info katanaqp_board_info[] = {
+
+	[KATANAQP_CFG_PRPMC_SINGLE] = {
+		.cfg_name = "PrPMC Single Core",
+		.eth_phys = {10, 13, 6},
+	},
+
+	[KATANAQP_CFG_PRPMC_DUAL] = {
+		.cfg_name = "PrPMC Dual Core",
+		.eth_phys = {10, 13, 6}
+	},
+
+	[KATANAQP_CFG_PT2CC_SINGLE] = {
+		.cfg_name = "PT2CC Single Core",
+		.eth_phys = {9, 8, 6},
+	},
+
+	[KATANAQP_CFG_PT5CC_SINGLE] = {
+		.cfg_name = "PT5CC Single Core",
+		.eth_phys = {10, 13, 6},
+	},
+
+	[KATANAQP_CFG_MEDIA_DUAL] = {
+		.cfg_name = "Dual Core Media Blade",
+		.eth_phys = {10, 13, 6},
+	},
+
+	[KATANAQP_CFG_PT2CC_DUAL] = {
+		.cfg_name = "PT2CC Dual Core",
+		.eth_phys = {9, 8, 6},
+	},
+
+	[KATANAQP_CFG_PT5CC_DUAL] = {
+		.cfg_name = "PT5CC Dual Core",
+		.eth_phys = {10, 13, 6},
+	},
+
+	[KATANAQP_CFG_MEDIA_SINGLE] = {
+		.cfg_name = "Single Core Media Blade",
+		.eth_phys = {10, 13, 6},
+	},
+};
+
+/*
+ * Second flash bank partition layout.
+ */
+static struct katanaqp_mtd_part katanaqp_mtd_parts[MTD_PART_NUM] = {
+	{
+		.name = "Secondary Monitor",
+		.size = MTD_PART_MONITOR_SIZE,
+		.ro = 1,
+	},
+
+	{
+		.name = "Secondary Kernel",
+		.size = MTD_PART_KERNEL_SIZE,
+	},
+
+	{
+		/* Size depends on actual flash bank size */
+		.name = "Secondary FS",
+	},
+};
+
+static u8 *katanaqp_get_cpld_base(void)
+{
+	u32 v;
+	void *devp;
+
+	devp = finddevice("cpld");
+	if (devp == NULL)
+		fatal("Error: Missing CPLD device tree node\n\r");
+
+	if (getprop(devp, "virtual-reg", &v, sizeof(v)) != sizeof(v))
+		fatal("Error: Can't get CPLD base address\n\r");
+
+	return (u8 *) v;
+}
+
+static void katanaqp_get_cfg(void)
+{
+	katanaqp_cfg = in_8(cpld_base + KATANAQP_CPLD_HCR) & 0xf;
+
+	if (katanaqp_cfg > 9)
+		katanaqp_cfg = KATANAQP_UNKNOWN;
+}
+
+static int katanaqp_is_monarch(void)
+{
+	return !(in_8(cpld_base + KATANAQP_CPLD_PSR) &
+		 KATANAQP_CPLD_PSR_PMCM);
+}
+
+static void katanaqp_bridge_setup(void)
+{
+	u32 i, v[12], enables, acc_bits;
+	u32 pci_base_hi, pci_base_lo, size, buf[2];
+	unsigned long cpu_base;
+	int rc;
+	void *devp;
+	u8 *bridge_pbase, is_coherent;
+	struct mv64x60_cpu2pci_win *tbl;
+
+	bridge_pbase = mv64x60_get_bridge_pbase();
+	is_coherent = mv64x60_is_coherent();
+
+	if (is_coherent)
+		acc_bits = MV64x60_PCI_ACC_CNTL_SNOOP_WB
+		    | MV64x60_PCI_ACC_CNTL_SWAP_NONE
+		    | MV64x60_PCI_ACC_CNTL_MBURST_32_BYTES
+		    | MV64x60_PCI_ACC_CNTL_RDSIZE_32_BYTES;
+	else
+		acc_bits = MV64x60_PCI_ACC_CNTL_SNOOP_NONE
+		    | MV64x60_PCI_ACC_CNTL_SWAP_NONE
+		    | MV64x60_PCI_ACC_CNTL_MBURST_128_BYTES
+		    | MV64x60_PCI_ACC_CNTL_RDSIZE_256_BYTES;
+
+	/*
+	 * MV64x60 boot code expects PCI host bridge to have 0 device
+	 * number and access PCI configuration bridge registers by
+	 * DEVFN(0, fn). This is not correct for bridges working in PCI-X
+	 * mode since by default it has 0x1f device number stored in P2P
+	 * configuration register.
+	 */
+	mv64x60_set_pci_bus(bridge_base, 1, 0, 0);
+	
+	mv64x60_config_ctlr_windows(bridge_base, bridge_pbase, is_coherent);
+	mv64x60_config_pci_windows(bridge_base, bridge_pbase, 1, 0, acc_bits);
+
+	/* Get the cpu -> pci i/o & mem mappings from the device tree */
+	devp = finddevice("/mv64x60/pci");
+	if (devp == NULL)
+		fatal("Error: Missing /mv64x60/pci device tree node\n\r");
+
+	rc = getprop(devp, "ranges", v, sizeof(v));
+	if (rc != sizeof(v))
+		fatal("Error: Can't find /mv64x60/pci/ranges property\n\r");
+
+	/* Get the cpu -> pci i/o & mem mappings from the device tree */
+	devp = finddevice("/mv64x60");
+	if (devp == NULL)
+		fatal("Error: Missing /mv64x60 device tree node\n\r");
+
+
+	enables = in_le32((u32 *) (bridge_base + MV64x60_CPU_BAR_ENABLE));
+	enables |= 0x0007fe00;	/* Disable all cpu->pci windows */
+	out_le32((u32 *) (bridge_base + MV64x60_CPU_BAR_ENABLE), enables);
+
+	for (i = 0; i < 12; i += 6) {
+		switch (v[i] & 0xff000000) {
+		case 0x01000000:	/* PCI I/O Space */
+			tbl = mv64x60_cpu2pci_io;
+			break;
+		case 0x02000000:	/* PCI MEM Space */
+			tbl = mv64x60_cpu2pci_mem;
+			break;
+		default:
+			continue;
+		}
+
+		pci_base_hi = v[i + 1];
+		pci_base_lo = v[i + 2];
+		cpu_base = v[i + 3];
+		size = v[i + 5];
+
+		buf[0] = cpu_base;
+		buf[1] = size;
+
+		if (!dt_xlate_addr(devp, buf, sizeof(buf), &cpu_base))
+			fatal("Error: Can't translate PCI address 0x%x\n\r",
+			      (u32) cpu_base);
+
+		mv64x60_config_cpu2pci_window(bridge_base, 1, pci_base_hi,
+					      pci_base_lo, cpu_base, size, tbl);
+	}
+
+	/* Enable cpu->pci1 i/o, cpu->pci1 mem0 */
+	enables &= ~0x0000c000;
+	out_le32((u32 *) (bridge_base + MV64x60_CPU_BAR_ENABLE), enables);
+
+}
+
+/*
+ * Different Katana Qp configurations have different flash sizes varying
+ * from 16Mb to 64Mb. This routine determines an exact flash size and
+ * updates the device tree accordingly.
+ */
+static void katanaqp_flash_fixup(void)
+{
+	u32 flash0_size = 0, flash1_size = 0;
+	u32 total_size, size_left;
+	u32 part, part_offset;
+	u32 rc, v[2];
+	void *devp = NULL, *pp = NULL;
+	char part_node[MTD_PART_NODE_LEN];
+
+	devp = finddevice("/mv64x60/flash");
+	if (devp == NULL) {
+		printf("Missing flash device tree node\n\r");
+		return;
+	}
+
+	/*
+	 * Get fist flash size: bank0, bank1 and total
+	 */
+	flash0_size = mv64x60_get_devcs_size(bridge_base, 0);
+	if (flash0_size == 0)
+		return;
+
+	flash1_size = mv64x60_get_devcs_size(bridge_base, 1);
+	total_size = flash0_size + flash1_size;
+
+	/*
+	 * Set total flash size
+	 */
+	rc = getprop(devp, "reg", v, sizeof(v));
+	if (rc != sizeof(v))
+		fatal("Error: Can't find /mv64x60/flash/reg property\n\r");
+	v[1] = total_size;
+	setprop(devp, "reg", v, sizeof(v));
+
+	/*
+	 * Set Primary FS partition size: up to the end of first flash bank
+	 */
+	pp = find_node_by_prop_value_str(NULL, "label", "Primary FS");
+	if (pp == NULL)
+		fatal("Error: Missing flash Primary FS device tree node\n\r");
+
+	rc = getprop(pp, "reg", v, sizeof(v));
+	if (rc != sizeof(v))
+		fatal("Error: Can't find /mv64x60/flash/partition@3000000 "
+		      "property\n\r");
+
+	v[1] = flash0_size - MTD_PART_MONITOR_SIZE - MTD_PART_KERNEL_SIZE;
+	setprop(pp, "reg", v, sizeof(v));
+
+	if (flash1_size == 0)
+		/* Only 1 flash bank is presented */
+		return;
+
+	/*
+	 * Ok, there is a second flash bank. Let's split it to partitions.
+	 */
+
+	part_offset = flash0_size;
+	size_left = flash1_size;
+
+	/* Skip Secondary Monitor if Boot Failover mechanism is disabled */
+	rc = in_8(cpld_base + KATANAQP_CPLD_JSR) & KATANAQP_CPLD_JSR_EBFM;
+	part = rc ? 0 : 1;
+
+	for (; part < MTD_PART_NUM; part++) {
+
+		sprintf(part_node, "%s@%x", MTD_PART_NODE, part_offset);
+		pp = create_node(devp, part_node);
+		if (pp == NULL)
+			fatal("Error: Can't create new partition node\n\r");
+
+		setprop_str(pp, "label", katanaqp_mtd_parts[part].name);
+
+		if (katanaqp_mtd_parts[part].ro)
+			setprop(pp, "read-only", NULL, 0);
+
+		v[0] = part_offset;
+		v[1] = katanaqp_mtd_parts[part].size;
+		if (v[1] == 0)
+			/* Take all remaining space */
+			v[1] = size_left;
+
+		part_offset += v[1];
+		size_left -= v[1];
+
+		setprop(pp, "reg", v, sizeof(v));
+
+	}
+}
+
+static void katanaqp_fixups(void)
+{
+	u32 l, p, pnum;
+	void *devp = NULL;
+	struct katanaqp_board_info katanaqp_bif;
+	char model[BOARD_MODEL_LEN];
+
+	/* Check Katana Qp configuration */
+	katanaqp_get_cfg();
+	if (katanaqp_cfg == KATANAQP_CFG_UNKNOWN)
+		fatal("Error: Unsupported Katana Qp board configuration\n\r");
+
+	if (katanaqp_cfg == KATANAQP_CFG_PT5CC_CUSTOM) {
+		printf("Katana Qp board custom configuration detected, "
+		       "using device tree defaults. Please, supply a correct "
+		       "device tree\n\r");
+		return;
+	}
+
+	katanaqp_bif = katanaqp_board_info[katanaqp_cfg];
+
+	/*
+	 * Set /model appropriately
+	 */
+	devp = finddevice("/");
+	if (devp == NULL)
+		fatal("Error: Missing '/' device tree node\n\r");
+
+	/*
+	 * Fix Board model name in device tree
+	 */
+	memset(model, 0, BOARD_MODEL_LEN);
+
+	strncpy(model, BOARD_MODEL, BOARD_MODEL_MAX - 1);
+	l = strlen(model);
+	model[l++] = ' ';
+
+	strncpy(&model[l], katanaqp_bif.cfg_name, BOARD_CFG_MAX - 1);
+	l += strlen(&model[l]);
+	model[l++] = '\0';
+
+	setprop(devp, "model", model, l);
+
+	/*
+	 * Do necessary bridge setup if we are monarch
+	 */
+	if (katanaqp_is_monarch())
+		katanaqp_bridge_setup();
+
+	/*
+	 * Fix RAM size and setup MV64460 bridge
+	 */
+	dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
+
+	/*
+	 * Fix flash size and partition layout
+	 */
+	katanaqp_flash_fixup();
+
+	/*
+	 * Fix clocks
+	 */
+	dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 4, bd.bi_busfreq);
+
+	/*
+	 * Fix phy addresses
+	 */
+	while ((devp = find_node_by_prop_value_str(devp, "comaptible",
+						   "marvell,mv88e1111"))) {
+		getprop(devp, "block-index", &p, sizeof(p));
+		pnum = katanaqp_bif.eth_phys[p];
+		setprop_val(devp, "reg", pnum);
+	}
+}
+
+static void katanaqp_reset(void)
+{
+
+	/* issue hard reset to the reset command register */
+	if (cpld_base)
+		out_8(cpld_base + KATANAQP_CPLD_RCR,
+		      KATANAQP_CPLD_RCR_CPUHR);
+
+	for (;;) ;
+}
+
+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+		   unsigned long r6, unsigned long r7)
+{
+
+	CUBOOT_INIT();
+
+	if (ft_init(_dtb_start, _dtb_end - _dtb_start, 16))
+		exit();
+
+	bridge_base = mv64x60_get_bridge_base();
+	cpld_base = katanaqp_get_cpld_base();
+
+	platform_ops.fixups = katanaqp_fixups;
+	platform_ops.exit = katanaqp_reset;
+
+	if (serial_console_init() < 0)
+		exit();
+}

[PATCH 4/5] PowerPC 74xx: Katana Qp base support

[Andrei Dolnikov]

Emerson Katana Qp platform specific code

Signed-off-by: Andrei Dolnikov <adolnikov@ru.mvista.com>

---
 Kconfig    |    9 +++
 Makefile   |    1
 katanaqp.c |  168 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 178 insertions(+)

diff --git a/arch/powerpc/platforms/embedded6xx/Kconfig b/arch/powerpc/platforms/embedded6xx/Kconfig
index 8924095..33190bd 100644
--- a/arch/powerpc/platforms/embedded6xx/Kconfig
+++ b/arch/powerpc/platforms/embedded6xx/Kconfig
@@ -46,6 +46,15 @@ config PPC_PRPMC2800
 	help
 	  This option enables support for the Motorola PrPMC2800 board
 
+config PPC_KATANAQP
+	bool "Emerson-Katana Qp"
+	depends on EMBEDDED6xx
+	select MV64X60
+	select NOT_COHERENT_CACHE
+	select WANT_DEVICE_TREE
+	help
+	  This option enables support for the Emerson Katana Qp board
+
 config TSI108_BRIDGE
 	bool
 	depends on MPC7448HPC2 || PPC_HOLLY
diff --git a/arch/powerpc/platforms/embedded6xx/Makefile b/arch/powerpc/platforms/embedded6xx/Makefile
index 844947c..c83558f 100644
--- a/arch/powerpc/platforms/embedded6xx/Makefile
+++ b/arch/powerpc/platforms/embedded6xx/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_MPC7448HPC2)	+= mpc7448_hpc2.o
 obj-$(CONFIG_LINKSTATION)	+= linkstation.o ls_uart.o
 obj-$(CONFIG_PPC_HOLLY)		+= holly.o
 obj-$(CONFIG_PPC_PRPMC2800)	+= prpmc2800.o
+obj-$(CONFIG_PPC_KATANAQP)	+= katanaqp.o
diff --git a/arch/powerpc/platforms/embedded6xx/katanaqp.c b/arch/powerpc/platforms/embedded6xx/katanaqp.c
new file mode 100644
index 0000000..64fb608
--- /dev/null
+++ b/arch/powerpc/platforms/embedded6xx/katanaqp.c
@@ -0,0 +1,168 @@
+/*
+ * Board setup routines for the Emerson Katana Qp
+ *
+ * Authors: Vladislav Buzov <vbuzov@ru.mvista.com>
+ *	    Andrei Dolnikov <adolnikov@ru.mvista.com>
+ *
+ * Based on prpmc2800.c by Dale Farnsworth <dale@farnsworth.org>
+ *
+ * 2007 (c) MontaVista, Software, Inc.  This file is licensed under
+ * the terms of the GNU General Public License version 2.  This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/seq_file.h>
+#include <linux/of_platform.h>
+#include <linux/pci.h>
+
+#include <asm/machdep.h>
+#include <asm/prom.h>
+#include <asm/system.h>
+#include <asm/time.h>
+#include <asm/kexec.h>
+
+#include <mm/mmu_decl.h>
+
+#include <sysdev/mv64x60.h>
+
+#define PLATFORM_NAME_MAX	64
+
+/* CPLD registers definitions */
+#define KATANAQP_CPLD_RCR	0x0004	/* Reset command */
+#define KATANAQP_CPLD_RCR_CPUHR	(1 << 7)
+
+#define KATANAQP_CPLD_HVR	0x0020
+
+#define KATANAQP_CPLD_PSR	0x0030	/* PCI status */
+#define KATANAQP_CPLD_PSR_PMCM	(1 << 1)
+
+#define KATANAQP_CPLD_HCR	0x0044
+
+static char katanaqp_platform_name[PLATFORM_NAME_MAX];
+
+static void __iomem *cpld_base;
+
+static int katanaqp_exclude_device(struct pci_controller *hose, u_char bus,
+			    u_char devfn)
+{
+	if (bus == 0 && PCI_SLOT(devfn) == 0)
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	else
+		return PCIBIOS_SUCCESSFUL;
+}
+
+static int __init katanaqp_is_monarch(void)
+{
+	return !(in_8(cpld_base + KATANAQP_CPLD_PSR) &
+		 KATANAQP_CPLD_PSR_PMCM);
+}
+
+static void __init katanaqp_setup_arch(void)
+{
+	struct device_node *cpld;
+
+	/*
+	 * ioremap cpld registers in case they are later
+	 * needed by katanaqp_reset_board().
+	 */
+	cpld = of_find_compatible_node(NULL, NULL, "altera,maxii");
+	cpld_base = of_iomap(cpld, 0);
+
+#ifdef CONFIG_PCI
+	if (katanaqp_is_monarch()) {
+		mv64x60_pci_init();
+		ppc_md.pci_exclude_device = katanaqp_exclude_device;
+	}
+#endif
+
+	printk("Emerson Network Power %s\n", katanaqp_platform_name);
+}
+
+static void katanaqp_reset_board(void)
+{
+	local_irq_disable();
+
+	/* issue hard reset to the reset command register */
+	out_8(cpld_base + KATANAQP_CPLD_RCR, KATANAQP_CPLD_RCR_CPUHR);
+	for (;;) ;
+}
+
+static void katanaqp_restart(char *cmd)
+{
+	katanaqp_reset_board();
+}
+
+static void katanaqp_show_cpuinfo(struct seq_file *m)
+{
+	uint memsize = total_memory;
+
+	seq_printf(m, "vendor\t\t: Emerson Network Power\n");
+
+	seq_printf(m, "hardware rev\t: %d\n",
+		   in_8(cpld_base + KATANAQP_CPLD_HVR));
+
+	seq_printf(m, "hardware config\t: %d\n",
+		   in_8(cpld_base + KATANAQP_CPLD_HCR));
+
+	seq_printf(m, "memory size\t: %d MB\n", memsize / (1024 * 1024));
+
+	seq_printf(m, "PCI\t\t: %sMonarch\n",
+		   katanaqp_is_monarch() ? "" : "Non-");
+}
+
+static int __init katanaqp_of_init(void)
+{
+	struct device_node *np;
+
+	np = of_find_compatible_node(NULL, NULL, "cfi-flash");
+	if (np)
+		of_platform_device_create(np, "of-flash", NULL);
+
+	return 0;
+}
+
+device_initcall(katanaqp_of_init);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init katanaqp_probe(void)
+{
+	unsigned long root = of_get_flat_dt_root();
+	unsigned long len;
+	void *m;
+
+	if (!of_flat_dt_is_compatible(root, "emerson,Katana-Qp"))
+		return 0;
+
+	/* Update ppc_md.name with name from dt */
+	m = of_get_flat_dt_prop(root, "model", &len);
+	if (m)
+		strncpy(katanaqp_platform_name, m,
+			min((int)len, PLATFORM_NAME_MAX - 1));
+
+	return 1;
+}
+
+define_machine(katanaqp)
+{
+	.name			= katanaqp_platform_name,
+	.probe			= katanaqp_probe,
+	.setup_arch		= katanaqp_setup_arch,
+	.init_early		= mv64x60_init_early,
+	.show_cpuinfo		= katanaqp_show_cpuinfo,
+	.init_IRQ		= mv64x60_init_irq,
+	.get_irq		= mv64x60_get_irq,
+	.restart		= katanaqp_restart,
+	.calibrate_decr		= generic_calibrate_decr,
+#ifdef CONFIG_KEXEC
+	.machine_kexec		= default_machine_kexec,
+	.machine_kexec_prepare	= default_machine_kexec_prepare,
+	.machine_crash_shutdown	= default_machine_crash_shutdown,
+#endif
+};

[PATCH 5/5] PowerPC 74xx: Katana Qp default config

[Andrei Dolnikov]

Default kernel config for Emerson Katana Qp board

Signed-off-by: Andrei Dolnikov <adolnikov@ru.mvista.com>

---
 katanaqp_defconfig |  941 +++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 941 insertions(+)

diff --git a/arch/powerpc/configs/katanaqp_defconfig b/arch/powerpc/configs/katanaqp_defconfig
new file mode 100644
index 0000000..7ea32ca
--- /dev/null
+++ b/arch/powerpc/configs/katanaqp_defconfig
@@ -0,0 +1,941 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.24-rc2
+# Tue Nov 13 16:02:34 2007
+#
+# CONFIG_PPC64 is not set
+
+#
+# Processor support
+#
+CONFIG_6xx=y
+# CONFIG_PPC_85xx is not set
+# CONFIG_PPC_8xx is not set
+# CONFIG_40x is not set
+# CONFIG_44x is not set
+# CONFIG_E200 is not set
+CONFIG_PPC_FPU=y
+CONFIG_ALTIVEC=y
+CONFIG_PPC_STD_MMU=y
+CONFIG_PPC_STD_MMU_32=y
+# CONFIG_PPC_MM_SLICES is not set
+# CONFIG_SMP is not set
+CONFIG_NOT_COHERENT_CACHE=y
+CONFIG_CHECK_CACHE_COHERENCY=y
+CONFIG_PPC32=y
+CONFIG_WORD_SIZE=32
+CONFIG_PPC_MERGE=y
+CONFIG_MMU=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_IRQ_PER_CPU=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_ARCH_HAS_ILOG2_U32=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
+CONFIG_PPC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_PPC_OF=y
+CONFIG_OF=y
+# CONFIG_PPC_UDBG_16550 is not set
+# CONFIG_GENERIC_TBSYNC is not set
+CONFIG_AUDIT_ARCH=y
+CONFIG_GENERIC_BUG=y
+# CONFIG_DEFAULT_UIMAGE is not set
+# CONFIG_PPC_DCR_NATIVE is not set
+# CONFIG_PPC_DCR_MMIO is not set
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+# CONFIG_MODULES is not set
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+
+#
+# Platform support
+#
+CONFIG_PPC_MULTIPLATFORM=y
+# CONFIG_PPC_82xx is not set
+# CONFIG_PPC_83xx is not set
+# CONFIG_PPC_86xx is not set
+CONFIG_CLASSIC32=y
+# CONFIG_PPC_CHRP is not set
+# CONFIG_PPC_MPC52xx is not set
+# CONFIG_PPC_MPC5200 is not set
+# CONFIG_PPC_EFIKA is not set
+# CONFIG_PPC_LITE5200 is not set
+# CONFIG_PPC_PMAC is not set
+# CONFIG_PPC_CELL is not set
+# CONFIG_PPC_CELL_NATIVE is not set
+# CONFIG_PQ2ADS is not set
+CONFIG_EMBEDDED6xx=y
+# CONFIG_LINKSTATION is not set
+# CONFIG_MPC7448HPC2 is not set
+# CONFIG_PPC_HOLLY is not set
+# CONFIG_PPC_PRPMC2800 is not set
+CONFIG_PPC_KATANAQP=y
+CONFIG_MV64X60=y
+# CONFIG_MPIC is not set
+# CONFIG_MPIC_WEIRD is not set
+# CONFIG_PPC_I8259 is not set
+# CONFIG_PPC_RTAS is not set
+# CONFIG_MMIO_NVRAM is not set
+# CONFIG_PPC_MPC106 is not set
+# CONFIG_PPC_970_NAP is not set
+# CONFIG_PPC_INDIRECT_IO is not set
+# CONFIG_GENERIC_IOMAP is not set
+# CONFIG_CPU_FREQ is not set
+# CONFIG_TAU is not set
+# CONFIG_CPM2 is not set
+# CONFIG_FSL_ULI1575 is not set
+
+#
+# Kernel options
+#
+CONFIG_HIGHMEM=y
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_BINFMT_ELF=y
+CONFIG_BINFMT_MISC=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+# CONFIG_KEXEC is not set
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_PROC_DEVICETREE=y
+# CONFIG_CMDLINE_BOOL is not set
+# CONFIG_PM is not set
+CONFIG_SUSPEND_UP_POSSIBLE=y
+CONFIG_HIBERNATION_UP_POSSIBLE=y
+# CONFIG_SECCOMP is not set
+CONFIG_WANT_DEVICE_TREE=y
+CONFIG_DEVICE_TREE="katanaqp.dts"
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_ZONE_DMA=y
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_PPC_INDIRECT_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_SYSCALL=y
+# CONFIG_PCIEPORTBUS is not set
+CONFIG_ARCH_SUPPORTS_MSI=y
+# CONFIG_PCI_MSI is not set
+CONFIG_PCI_LEGACY=y
+# CONFIG_PCCARD is not set
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_HIGHMEM_START=0xfe000000
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_TASK_SIZE=0xc0000000
+CONFIG_CONSISTENT_START=0xff100000
+CONFIG_CONSISTENT_SIZE=0x00200000
+CONFIG_BOOT_LOAD=0x00800000
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=y
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_2 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+# CONFIG_MTD_CFI_I1 is not set
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+CONFIG_OF_DEVICE=y
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=131072
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_NSP32 is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_SRP is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+# CONFIG_MACINTOSH_DRIVERS is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_IP1000 is not set
+# CONFIG_ARCNET is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_EEPRO100 is not set
+CONFIG_E100=y
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_8139CP is not set
+CONFIG_8139TOO=y
+# CONFIG_8139TOO_PIO is not set
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139TOO_8129 is not set
+# CONFIG_8139_OLD_RX_RESET is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_SC92031 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+CONFIG_E1000=y
+# CONFIG_E1000_NAPI is not set
+# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
+# CONFIG_E1000E is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+CONFIG_MV643XX_ETH=y
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+CONFIG_NETDEV_10000=y
+# CONFIG_CHELSIO_T1 is not set
+# CONFIG_CHELSIO_T3 is not set
+# CONFIG_IXGBE is not set
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+# CONFIG_MYRI10GE is not set
+# CONFIG_NETXEN_NIC is not set
+# CONFIG_NIU is not set
+# CONFIG_MLX4_CORE is not set
+# CONFIG_TEHUTI is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_MPSC=y
+CONFIG_SERIAL_MPSC_CONSOLE=y
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+CONFIG_GEN_RTC=y
+# CONFIG_GEN_RTC_X is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_VGA_CONSOLE=y
+# CONFIG_VGACON_SOFT_SCROLLBACK is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_INFINIBAND is not set
+# CONFIG_EDAC is not set
+# CONFIG_RTC_CLASS is not set
+
+#
+# Userspace I/O
+#
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+# CONFIG_UCC_SLOW is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_INSTRUMENTATION=y
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_SAMPLES is not set
+# CONFIG_BOOTX_TEXT is not set
+# CONFIG_PPC_EARLY_DEBUG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+# CONFIG_PPC_CLOCK is not set

Re: [PATCH 1/5] PowerPC 74xx: Katana Qp device tree

[David Gibson]

On Thu, Nov 29, 2007 at 06:28:36PM +0300, Andrei Dolnikov wrote:
> Device tree source file for the Emerson Katana Qp board
> 
> Signed-off-by: Andrei Dolnikov <adolnikov@ru.mvisa.com>
> 
> ---
>  katanaqp.dts |  360 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
>  1 files changed, 360 insertions(+)
> 
> diff --git a/arch/powerpc/boot/dts/katanaqp.dts b/arch/powerpc/boot/dts/katanaqp.dts
> new file mode 100644
> index 0000000..98257a2
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/katanaqp.dts
> @@ -0,0 +1,360 @@
> +/* Device Tree Source for Emerson Katana Qp
> + *
> + * Authors: Vladislav Buzov <vbuzov@ru.mvista.com>
> + *	    Andrei Dolnikov <adolnikov@ru.mvista.com>
> + * 
> + * Based on prpmc8200.dts by Mark A. Greer <mgreer@mvista.com>
> + *
> + * 2007 (c) MontaVista, Software, Inc.  This file is licensed under
> + * the terms of the GNU General Public License version 2.  This program
> + * is licensed "as is" without any warranty of any kind, whether express
> + * or implied.
> + *
> + */
> +
> +/ {
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	model = "Katana-Qp"; /* Default */
> +	compatible = "emerson,Katana-Qp";
> +	coherency-off;

What is this property for?

> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		PowerPC,7448@0 {
> +			device_type = "cpu";
> +			reg = <0>;
> +			clock-frequency = <0>;		/* From U-boot */
> +			bus-frequency = <0>;		/* From U-boot */
> +			timebase-frequency = <0>;	/* From U-boot */
> +			i-cache-line-size = <20>;
> +			d-cache-line-size = <20>;
> +			i-cache-size = <8000>;
> +			d-cache-size = <8000>;
> +		};
> +	};
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <00000000 00000000>;	/* Filled in by bootwrapper */
> +	};
> +
> +	mv64x60@f8100000 { /* Marvell Discovery */
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		model = "mv64460";			/* Default */
> +		compatible = "marvell,mv64x60";

Compatible properties should not have "x" asn in 64x60 here.  If
there's a suitable name for the general register interface use that,
otherwise use the specific model number of the earliest device to
implement this register interface.  Later models should have a
compatible property which lists their specific model, followed by the
earlier model number with which they're compatible.

> +		clock-frequency = <7f28155>;		/* 133.333333 MHz */

You can use <d# 133333333> to avoid the ugly hex.

> +		reg = <f8100000 00010000>;
> +		virtual-reg = <f8100000>;
> +		ranges = <c1000000 c1000000 01000000	/* PCI 1 I/O Space */
> +			  90000000 90000000 30000000	/* PCI 1 MEM Space */
> +			  e8000000 e8000000 04000000	/* User FLASH: Up to 64Mb */
> +			  00000000 f8100000 00010000	/* Bridge's regs */
> +			  f8500000 f8500000 00040000>;	/* Integrated SRAM */

These ranges look kind of weird, but I'd have to think about them
harder to say something more specific.

> +		flash@e8000000 {
> +			compatible = "cfi-flash";
> +			reg = <e8000000 1000000>; /* Default (16MB) */
> +			probe-type = "CFI";

You're using the new-style binding (compatible == "cfi-flash"), so the
obsolete probe-tyope property should not be included.

> +			bank-width = <4>;
> +			
> +			partition@0 {
> +				label = "Primary Monitor";
> +				reg = <0 100000>; /* 1Mb */
> +				read-only;
> +			};
> +
> +			partition@100000 {
> +				label = "Primary Kernel";
> +				reg = <100000 200000>; /* 2 Mb */
> +			};
> +
> +			partition@300000 {
> +				label = "Primary FS";
> +				reg = <300000 d00000>; /* 13 Mb */
> +			};
> +
> +		};
> +
> +		mdio {

There must be some way of actuall accessing the mdio bus, so this node
ought to have a 'reg' property and unit address.

> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			compatible = "marvell,mv64x60-mdio";
> +			ethernet-phy@0 {
> +				block-index = <0>;
> +				compatible = "marvell,mv88e1111";
> +				reg = <a>;
> +			};
> +			ethernet-phy@1 {
> +				compatible = "marvell,mv88e1111";
> +				block-index = <1>;
> +				reg = <d>;
> +			};
> +			ethernet-phy@2 {
> +				compatible = "marvell,mv88e1111";
> +				block-index = <2>;
> +				reg = <6>;
> +			};
> +		};
> +
> +		ethernet@2000 {
> +			reg = <2000 2000>;

Are the registers for the 3 ethernets really all together?  This bank
can't be subdivided into seperate register blocks for each MAC?

> +			eth0 {
> +				device_type = "network";
> +				compatible = "marvell,mv64x60-eth";
> +				block-index = <0>;

This block-index thing is crap.  If you really need to subindex nodes
like this, use "reg", with an appropriate #address-cells in the
parent, then the nodes will also get sensible unit addresses.

> +				interrupts = <20>;
> +				interrupt-parent = <&/mv64x60/pic>;

You should use a label for the PIC to make things more readable.

> +				phy = <&/mv64x60/mdio/ethernet-phy@0>;
> +				speed = <3e8>; 
> +				duplex = <1>; 
> +				tx_queue_size = <320>;
> +				rx_queue_size = <190>;
> +				local-mac-address = [ 00 00 00 00 00 00 ];
> +				/* Mac address filled in by bootwrapper */
> +			};
> +			eth1 {
> +				device_type = "network";
> +				compatible = "marvell,mv64x60-eth";
> +				block-index = <1>;
> +				interrupts = <21>;
> +				interrupt-parent = <&/mv64x60/pic>;
> +				phy = <&/mv64x60/mdio/ethernet-phy@1>;
> +				speed = <3e8>; 
> +				duplex = <1>; 
> +				tx_queue_size = <320>;
> +				rx_queue_size = <190>;
> +				local-mac-address = [ 00 00 00 00 00 00 ];
> +				/* Mac address filled in by bootwrapper */
> +			};
> +			eth2 {
> +				device_type = "network";
> +				compatible = "marvell,mv64x60-eth";
> +				block-index = <2>;
> +				interrupts = <22>;
> +				interrupt-parent = <&/mv64x60/pic>;
> +				phy = <&/mv64x60/mdio/ethernet-phy@2>;
> +				speed = <3e8>; 
> +				duplex = <1>; 
> +				tx_queue_size = <320>;
> +				rx_queue_size = <190>;
> +				local-mac-address = [ 00 00 00 00 00 00 ];
> +				/* Mac address filled in by bootwrapper */
> +			};
> +		};
> +
> +		sdma@4000 {
> +			compatible = "marvell,mv64x60-sdma";
> +			reg = <4000 c18>;
> +			virtual-reg = <f8104000>;

Why does this node have virtual-reg?

> +			interrupt-base = <0>;
> +			interrupts = <24>;
> +			interrupt-parent = <&/mv64x60/pic>;
> +		};
> +
> +		sdma@6000 {
> +			compatible = "marvell,mv64x60-sdma";
> +			reg = <6000 c18>;
> +			virtual-reg = <f8106000>;

And again.

> +			interrupt-base = <0>;
> +			interrupts = <26>;
> +			interrupt-parent = <&/mv64x60/pic>;
> +		};
> +
> +		brg@b200 {
> +			compatible = "marvell,mv64x60-brg";
> +			reg = <b200 8>;
> +			clock-src = <8>;
> +			clock-frequency = <7ed6b40>;
> +			current-speed = <2580>;
> +			bcr = <0>;
> +		};
> +
> +		brg@b208 {
> +			compatible = "marvell,mv64x60-brg";
> +			reg = <b208 8>;
> +			clock-src = <8>;
> +			clock-frequency = <7ed6b40>;
> +			current-speed = <2580>;
> +			bcr = <0>;
> +		};
> +
> +		cunit@f200 {
> +			reg = <f200 200>;
> +		};
> +
> +		mpscrouting@b400 {
> +			reg = <b400 c>;
> +		};
> +
> +		mpscintr@b800 {
> +			reg = <b800 100>;
> +			virtual-reg = <f810b800>;
> +		};
> +
> +		mpsc@8000 {
> +			device_type = "serial";
> +			compatible = "marvell,mpsc";
> +			reg = <8000 38>;
> +			virtual-reg = <f8108000>;
> +			sdma = <&/mv64x60/sdma@4000>;
> +			brg = <&/mv64x60/brg@b200>;
> +			cunit = <&/mv64x60/cunit@f200>;
> +			mpscrouting = <&/mv64x60/mpscrouting@b400>;
> +			mpscintr = <&/mv64x60/mpscintr@b800>;
> +			block-index = <0>;

What is this block-index thing about here?  Since the devices are
disambiguated by their register address, why do you need it?

> +			max_idle = <28>;
> +			chr_1 = <0>;
> +			chr_2 = <0>;
> +			chr_10 = <3>;
> +			mpcr = <0>;
> +			interrupts = <28>;
> +			interrupt-parent = <&/mv64x60/pic>;
> +		};
> +
> +		mpsc@9000 {
> +			device_type = "serial";
> +			compatible = "marvell,mpsc";
> +			reg = <9000 38>;
> +			virtual-reg = <f8109000>;
> +			sdma = <&/mv64x60/sdma@6000>;
> +			brg = <&/mv64x60/brg@b208>;
> +			cunit = <&/mv64x60/cunit@f200>;
> +			mpscrouting = <&/mv64x60/mpscrouting@b400>;
> +			mpscintr = <&/mv64x60/mpscintr@b800>;
> +			block-index = <1>;
> +			max_idle = <28>;
> +			chr_1 = <0>;
> +			chr_2 = <0>;
> +			chr_10 = <3>;
> +			mpcr = <0>;
> +			interrupts = <29>; 
> +			interrupt-parent = <&/mv64x60/pic>;
> +		};
> +
> +		wdt@b410 {			/* watchdog timer */
> +			compatible = "marvell,mv64x60-wdt";
> +			reg = <b410 8>;
> +			timeout = <a>;		/* wdt timeout in seconds */

Uh... that looks like it should be a configuration parameter, not a
device tree property.

> +		};
> +
> +		i2c@c000 {
> +			compatible = "marvell,mv64x60-i2c";
> +			reg = <c000 20>;
> +			virtual-reg = <f810c000>;
> +			freq_m = <8>;
> +			freq_n = <3>;
> +			timeout = <3e8>;		/* 1000 = 1 second */
> +			retries = <1>;
> +			interrupts = <25>;
> +			interrupt-parent = <&/mv64x60/pic>;
> +		};
> +
> +		pic {

Needs a unit address.

> +			#interrupt-cells = <1>;
> +			#address-cells = <0>;
> +			compatible = "marvell,mv64x60-pic";
> +			reg = <0000 88>;
> +			interrupt-controller;
> +		};
> +
> +		mpp@f000 {
> +			compatible = "marvell,mv64x60-mpp";
> +			reg = <f000 10>;
> +		};
> +
> +		gpp@f100 {
> +			compatible = "marvell,mv64x60-gpp";
> +			reg = <f100 20>;
> +		};
> +
> +		pci@90000000 {
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +			#interrupt-cells = <1>;
> +			device_type = "pci";
> +			compatible = "marvell,mv64x60-pci";
> +			reg = <0c78 8>;
> +			ranges = <01000000 0        0 c1000000 0 01000000
> +				  02000000 0 90000000 90000000 0 30000000>;
> +			bus-range = <0 ff>;
> +			clock-frequency = <3EF1480>;
> +			interrupt-pci-iack = <0c34>;
> +			interrupt-parent = <&/mv64x60/pic>;
> +			interrupt-map-mask = <f800 0 0 7>;
> +			interrupt-map = <
> +				/* IDSEL 0x1 */
> +				0800 0 0 1 &/mv64x60/pic 5a
> +				0800 0 0 2 &/mv64x60/pic 5b
> +				0800 0 0 3 &/mv64x60/pic 5e
> +				0800 0 0 4 &/mv64x60/pic 5f
> +
> +				/* IDSEL 0x2 */
> +				1000 0 0 1 &/mv64x60/pic 5b
> +				1000 0 0 2 &/mv64x60/pic 5e
> +				1000 0 0 3 &/mv64x60/pic 5f
> +				1000 0 0 4 &/mv64x60/pic 5a
> +
> +				/* IDSEL 0x3 */
> +				1800 0 0 1 &/mv64x60/pic 5e
> +				1800 0 0 2 &/mv64x60/pic 5f
> +				1800 0 0 3 &/mv64x60/pic 5a
> +				1800 0 0 4 &/mv64x60/pic 5b
> +
> +				/* IDSEL 0x4 */
> +				2000 0 0 1 &/mv64x60/pic 5f
> +				2000 0 0 2 &/mv64x60/pic 5a
> +				2000 0 0 3 &/mv64x60/pic 5b
> +				2000 0 0 4 &/mv64x60/pic 5e
> +
> +				/* IDSEL 0x6 */
> +				3000 0 0 1 &/mv64x60/pic 5b
> +				3000 0 0 2 &/mv64x60/pic 5e
> +				3000 0 0 3 &/mv64x60/pic 5f
> +				3000 0 0 4 &/mv64x60/pic 5a
> +			>;
> +		};
> +
> +		cpu-error@0070 {

The unit address should notr include leading zeroes.

> +			compatible = "marvell,mv64x60-cpu-error";
> +			reg = <0070 10 0128 28>;
> +			interrupts = <03>;
> +			interrupt-parent = <&/mv64x60/pic>;
> +		};
> +
> +		sram-ctrl@0380 {
> +			compatible = "marvell,mv64x60-sram-ctrl";
> +			reg = <0380 80>;
> +			interrupts = <0d>;
> +			interrupt-parent = <&/mv64x60/pic>;
> +		};
> +
> +		pci-error@1d40 {
> +			compatible = "marvell,mv64x60-pci-error";
> +			reg = <1d40 40 0c28 4>;
> +			interrupts = <0c>;
> +			interrupt-parent = <&/mv64x60/pic>;
> +		};
> +
> +		mem-ctrl@1400 {
> +			compatible = "marvell,mv64x60-mem-ctrl";
> +			reg = <1400 60>;
> +			interrupts = <11>;
> +			interrupt-parent = <&/mv64x60/pic>;
> +		};
> +	};
> +
> +	cpld@f8200000 {
> +		compatible = "altera,maxii";
> +		reg = <f8200000 40000>;
> +		virtual-reg = <f8200000>;
> +	};
> +
> +	chosen {
> +		bootargs = "ip=on";
> +		linux,stdout-path = "/mv64x60@f8100000/mpsc@8000";
> +	};
> +};

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

Re: [PATCH 1/5] PowerPC 74xx: Katana Qp device tree

[Jon Loeliger]

On Sun, 2007-12-02 at 19:50, David Gibson wrote:

> > +		clock-frequency = <7f28155>;		/* 133.333333 MHz */
> You can use <d# 133333333> to avoid the ugly hex.

Better still, blaze a new trail, convert it to /dts-v1/ and
use clock-frequency = <133333333> straight up!


jdl

Re: [PATCH 1/5] PowerPC 74xx: Katana Qp device tree

[Benjamin Herrenschmidt]

> 	#address-cells = <1>;
> +	#size-cells = <1>;
> +	model = "Katana-Qp"; /* Default */
> +	compatible = "emerson,Katana-Qp";
> +	coherency-off;
> +

What do that mean (coherency-off) ?

Somebody is trying again to use a 74xx with non cache coherent DMA ?
That isn't going to fly...

Ben.
 

Re: [PATCH 4/5] PowerPC 74xx: Katana Qp base support

[Benjamin Herrenschmidt]

On Thu, 2007-11-29 at 18:42 +0300, Andrei Dolnikov wrote:
> +config PPC_KATANAQP
> +       bool "Emerson-Katana Qp"
> +       depends on EMBEDDED6xx
> +       select MV64X60
> +       select NOT_COHERENT_CACHE
                 ^^^^^^^^^^^^^^^^^^

Just one word: ARGHHHHHHHH !

Oh and another one: WHY ?

Ben.

Re: [PATCH 1/5] PowerPC 74xx: Katana Qp device tree

[David Gibson]

On Mon, Dec 03, 2007 at 01:26:34PM -0600, Jon Loeliger wrote:
> On Sun, 2007-12-02 at 19:50, David Gibson wrote:
> 
> > > +		clock-frequency = <7f28155>;		/* 133.333333 MHz */
> > You can use <d# 133333333> to avoid the ugly hex.
> 
> Better still, blaze a new trail, convert it to /dts-v1/ and
> use clock-frequency = <133333333> straight up!

Hrm.. probably best to wait for dtc to go into the kernel for that.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

Re: [PATCH 1/5] PowerPC 74xx: Katana Qp device tree

[Mark A. Greer]

On Tue, Dec 04, 2007 at 07:52:50AM +1100, Benjamin Herrenschmidt wrote:
> > 	#address-cells = <1>;
> > +	#size-cells = <1>;
> > +	model = "Katana-Qp"; /* Default */
> > +	compatible = "emerson,Katana-Qp";
> > +	coherency-off;
> > +
> 
> What do that mean (coherency-off) ?
> 
> Somebody is trying again to use a 74xx with non cache coherent DMA ?

Hi Ben.

I suspect Andrei got that from the prpmc2800 dts which I made so I'll
jump in.  (BTW, this is the same debate we have every year or two. :)

By looking at the dts, that board has an mv64460 which has a couple
issues when it comes to coherency (depending on the rev of the chip).

One is about not being able to use DCBST instructions with coherency on
and the other is about limiting the length of one of the traces (which
at least one board manufacturer that I know of refuses to implement).
The first one is supposed to be fixed by rev A1 of the part and the second
is supposed to be fixed by rev B0 of the part.  I don't know what rev(s)
are on the board(s) Andrei is using.  If its B0 or later, in theory, the
part should work with coherency on.

Andrei, have you tested with coherency on?

--

As far as the prpmc2800 (mv64360)...

[I don't know what an NDA let's me say or not so I'll just give
summaries of the errata.  If you or another reader has signed the NDA
you/they can look them up.]

I don't recall all of the details anymore but these are the errata I saw
by quickly scanning the 64360's list.

- "FEr CPU-#1":

Basically the CPU could read a stale cache line.  Supposed to be fixed
in rev A2 & B0 but I haven't verified.

- "FEr MPSC-#1":

The MPSC can't access a coherent memory region.
This is pretty much a show stopper for the prpmc2800.

There are no plans to fix that erratum.

- "FEr PCI-#4" (Detailed by Application Note AN-84):

[This isn't strictly a coherency issue but having coherency enabled
exacerbates the problem.]  Basically, the bridge can let the cpu read
a pci device's registers before all of the data the PCI devices has
written has actually made it to memory.  This and the fact that the
device's write data may be stuck in the PCI Slave Write Buffer
(which isn't checked for coherency), the cpu can get stale data.

There are no plans to fix that erratum.

- "FEr PCI-#5" (Detailed by Application Note AN-85):

With certain PCI devices and with coherency enabled, some combinations
of PCI transactions can cause a deadlock.  There is a workaround
documented but I've tried it and it didn't work for me (but I can't be
sure that was the erratum I was bumping into).

There are no plans to fix that erratum.
--

So, the answer depends on what part & what rev of the part you have
(e.g., the pegasos doesn't use the MPSC and apparently has the other
issues worked around so it can turn on coherency but the prpmc2800
doesn't so it needs coherency off).

BTW, I haven't forgotten the inherent bug you described when coherency
is off (/me too lazy to find link to the email) but AFAIK I've never run
into it.  However, if I turn on coherency and stress the PCI bus, it
hangs (I can't even look at memory thru a bdi).

Mark

Re: [PATCH 1/5] PowerPC 74xx: Katana Qp device tree

[Mark A. Greer]

On Mon, Dec 03, 2007 at 12:50:18PM +1100, David Gibson wrote:
> On Thu, Nov 29, 2007 at 06:28:36PM +0300, Andrei Dolnikov wrote:
> > Device tree source file for the Emerson Katana Qp board
> > 
> > Signed-off-by: Andrei Dolnikov <adolnikov@ru.mvisa.com>
> > 
> > ---
> >  katanaqp.dts |  360 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> >  1 files changed, 360 insertions(+)
> > 
> > diff --git a/arch/powerpc/boot/dts/katanaqp.dts b/arch/powerpc/boot/dts/katanaqp.dts
> > new file mode 100644
> > index 0000000..98257a2
> > --- /dev/null
> > +++ b/arch/powerpc/boot/dts/katanaqp.dts
> > @@ -0,0 +1,360 @@
> > +/* Device Tree Source for Emerson Katana Qp
> > + *
> > + * Authors: Vladislav Buzov <vbuzov@ru.mvista.com>
> > + *	    Andrei Dolnikov <adolnikov@ru.mvista.com>
> > + * 
> > + * Based on prpmc8200.dts by Mark A. Greer <mgreer@mvista.com>
> > + *
> > + * 2007 (c) MontaVista, Software, Inc.  This file is licensed under
> > + * the terms of the GNU General Public License version 2.  This program
> > + * is licensed "as is" without any warranty of any kind, whether express
> > + * or implied.
> > + *
> > + */
> > +
> > +/ {
> > +	#address-cells = <1>;
> > +	#size-cells = <1>;
> > +	model = "Katana-Qp"; /* Default */
> > +	compatible = "emerson,Katana-Qp";
> > +	coherency-off;
> 
> What is this property for?

Its needed to tell the bootwrapper that the platform does not have
coherency enabled (since our policy is that you can't use a CONFIG_ option).
The bootwrapper needs to know that if/when it sets up the windows for
its I/O devices (e.g., enet, mpsc) to system memory.  I needed to do
this on the prpmc2800 because the firmware didn't set up those windows
correctly.  I don't know if the Katana Qp's firmware sets the up
correctly or not.

> > +	mv64x60@f8100000 { /* Marvell Discovery */
> > +		#address-cells = <1>;
> > +		#size-cells = <1>;
> > +		model = "mv64460";			/* Default */
> > +		compatible = "marvell,mv64x60";
> 
> Compatible properties should not have "x" asn in 64x60 here.  If
> there's a suitable name for the general register interface use that,
> otherwise use the specific model number of the earliest device to
> implement this register interface.  Later models should have a
> compatible property which lists their specific model, followed by the
> earlier model number with which they're compatible.

This came from the prpmc2800's dts which has become out-of-date.
Both dts files need to be updated.

> > +		ethernet@2000 {
> > +			reg = <2000 2000>;
> 
> Are the registers for the 3 ethernets really all together?  This bank
> can't be subdivided into seperate register blocks for each MAC?

Unfortunately there are some registers that are shared so you can't
divide them up nicely.

> > +			eth0 {
> > +				device_type = "network";
> > +				compatible = "marvell,mv64x60-eth";
> > +				block-index = <0>;
> 
> This block-index thing is crap.  If you really need to subindex nodes
> like this, use "reg", with an appropriate #address-cells in the
> parent, then the nodes will also get sensible unit addresses.

So how would that work for the "PHY Address Register 0x2000", say,
where bits 0-4 set the device addr for PHY 0; bits 5-9 set the device
addr for PHY 1; bts 10-14 set the devce addr for PHY 2?

> > +				interrupts = <20>;
> > +				interrupt-parent = <&/mv64x60/pic>;
> 
> You should use a label for the PIC to make things more readable.

More that needs to be updated in prpmc2800.  :(

> > +		sdma@4000 {
> > +			compatible = "marvell,mv64x60-sdma";
> > +			reg = <4000 c18>;
> > +			virtual-reg = <f8104000>;
> 
> Why does this node have virtual-reg?

"virtual-reg" is a special property that doesn't get translated thru
the parent mappings.  It should never be used in the kernel.  Its
purpose is to give code in the bootwrapper the exact address that it
should use to access a register or block of registers or ...
Its needed here because the MPSC (serial) driver uses the SDMA unit
to perform console I/O in the bootwrapper (e.g., cmdline editing, printf's).

Yes, this needs to be documented.

> > +		mpsc@8000 {
> > +			device_type = "serial";
> > +			compatible = "marvell,mpsc";
> > +			reg = <8000 38>;
> > +			virtual-reg = <f8108000>;
> > +			sdma = <&/mv64x60/sdma@4000>;
> > +			brg = <&/mv64x60/brg@b200>;
> > +			cunit = <&/mv64x60/cunit@f200>;
> > +			mpscrouting = <&/mv64x60/mpscrouting@b400>;
> > +			mpscintr = <&/mv64x60/mpscintr@b800>;
> > +			block-index = <0>;
> 
> What is this block-index thing about here?  Since the devices are
> disambiguated by their register address, why do you need it?

This particular one is needed to access the correct MPSC interrupt reg.
Maybe it would be better to make a new property for this but it was only
one reg and block-index was already there and basically served that
purpose so I used it.  I'd be happy to use an alternative if you have
something you think is better.

> > +		pic {
> 
> Needs a unit address.

Okay.

> > +		cpu-error@0070 {
> 
> The unit address should notr include leading zeroes.

Okay.

Mark

Re: [PATCH 4/5] PowerPC 74xx: Katana Qp base support

[Mark A. Greer]

On Tue, Dec 04, 2007 at 07:54:59AM +1100, Benjamin Herrenschmidt wrote:
> 
> On Thu, 2007-11-29 at 18:42 +0300, Andrei Dolnikov wrote:
> > +config PPC_KATANAQP
> > +       bool "Emerson-Katana Qp"
> > +       depends on EMBEDDED6xx
> > +       select MV64X60
> > +       select NOT_COHERENT_CACHE
>                  ^^^^^^^^^^^^^^^^^^
> 
> Just one word: ARGHHHHHHHH !
> 
> Oh and another one: WHY ?

I responded to your other email regarding this.

Mark

Re: [PATCH 1/5] PowerPC 74xx: Katana Qp device tree

[Benjamin Herrenschmidt]

 .../... (snip scary bunch of errata)

> - "FEr PCI-#4" (Detailed by Application Note AN-84):
> 
> [This isn't strictly a coherency issue but having coherency enabled
> exacerbates the problem.]  Basically, the bridge can let the cpu read
> a pci device's registers before all of the data the PCI devices has
> written has actually made it to memory.  This and the fact that the
> device's write data may be stuck in the PCI Slave Write Buffer
> (which isn't checked for coherency), the cpu can get stale data.
> 
> There are no plans to fix that erratum.

So if I understand correctly, there's no plan to fix a major PCI spec
violation which prevent any kind of reliable implementation whatsoever ?

Or rather... the part just doesn't work, period. Don't use it. If you
do, you're on your own.

> - "FEr PCI-#5" (Detailed by Application Note AN-85):
> 
> With certain PCI devices and with coherency enabled, some combinations
> of PCI transactions can cause a deadlock.  There is a workaround
> documented but I've tried it and it didn't work for me (but I can't be
> sure that was the erratum I was bumping into).
> 
> There are no plans to fix that erratum.

Yeah... great. Oh well, Paul, what about we just don't support people
using that chip ?

> So, the answer depends on what part & what rev of the part you have
> (e.g., the pegasos doesn't use the MPSC and apparently has the other
> issues worked around so it can turn on coherency but the prpmc2800
> doesn't so it needs coherency off).
> 
> BTW, I haven't forgotten the inherent bug you described when coherency
> is off (/me too lazy to find link to the email) but AFAIK I've never run
> into it.  However, if I turn on coherency and stress the PCI bus, it
> hangs (I can't even look at memory thru a bdi).

Well, as it is today, the "classic" MMU code cannot deal with !coherent.
The entire linear mapping is always mapped cacheable with BATs, so stuff
may be brought into the cache at any time, potentially polluting DMA
data.

Dealing with that would be hard. It might be possible by using G on the
entire linear mapping like we do on 4xx (yuck), and/or by not using
D-BATs (the kernel will blow up in various areas without I-BATs).

Ben.

Re: [PATCH 1/5] PowerPC 74xx: Katana Qp device tree

[David Gibson]

On Mon, Dec 03, 2007 at 07:10:26PM -0700, Mark A. Greer wrote:
> On Mon, Dec 03, 2007 at 12:50:18PM +1100, David Gibson wrote:
> > On Thu, Nov 29, 2007 at 06:28:36PM +0300, Andrei Dolnikov wrote:
[snip]
> > > +		ethernet@2000 {
> > > +			reg = <2000 2000>;
> > 
> > Are the registers for the 3 ethernets really all together?  This bank
> > can't be subdivided into seperate register blocks for each MAC?
> 
> Unfortunately there are some registers that are shared so you can't
> divide them up nicely.

Ok, fair enough then.  But, see below..

> > > +			eth0 {
> > > +				device_type = "network";
> > > +				compatible = "marvell,mv64x60-eth";
> > > +				block-index = <0>;
> > 
> > This block-index thing is crap.  If you really need to subindex nodes
> > like this, use "reg", with an appropriate #address-cells in the
> > parent, then the nodes will also get sensible unit addresses.
> 
> So how would that work for the "PHY Address Register 0x2000", say,
> where bits 0-4 set the device addr for PHY 0; bits 5-9 set the device
> addr for PHY 1; bts 10-14 set the devce addr for PHY 2?

So use 'reg' to do the indexing.  As long as you have no 'ranges'
property in the parent 'ethernet' node, which you don't, you can use
'reg' as a private index.  That's basically what non-translatable reg
values are about.

Incidentally you should probably call the subnodes "ethernet@0"
etc. and the parent one "multiethernet" or something.  It's the
subnodes that represent an individual ethernet interface, so they
should take the "ethernet" name and not the parent, by generic names
conventions.

[snip]
> > > +		sdma@4000 {
> > > +			compatible = "marvell,mv64x60-sdma";
> > > +			reg = <4000 c18>;
> > > +			virtual-reg = <f8104000>;
> > 
> > Why does this node have virtual-reg?
> 
> "virtual-reg" is a special property that doesn't get translated thru
> the parent mappings.  It should never be used in the kernel.  Its
> purpose is to give code in the bootwrapper the exact address that it
> should use to access a register or block of registers or ...
> Its needed here because the MPSC (serial) driver uses the SDMA unit
> to perform console I/O in the bootwrapper (e.g., cmdline editing, printf's).
> 
> Yes, this needs to be documented.

Ok.  "it's used for serial in the bootwrapper" would have sufficed - I
questioned it because it wasn't obvious that this was needed to use
the mpsc.

> 
> > > +		mpsc@8000 {
> > > +			device_type = "serial";
> > > +			compatible = "marvell,mpsc";
> > > +			reg = <8000 38>;
> > > +			virtual-reg = <f8108000>;
> > > +			sdma = <&/mv64x60/sdma@4000>;
> > > +			brg = <&/mv64x60/brg@b200>;
> > > +			cunit = <&/mv64x60/cunit@f200>;
> > > +			mpscrouting = <&/mv64x60/mpscrouting@b400>;
> > > +			mpscintr = <&/mv64x60/mpscintr@b800>;
> > > +			block-index = <0>;
> > 
> > What is this block-index thing about here?  Since the devices are
> > disambiguated by their register address, why do you need it?
> 
> This particular one is needed to access the correct MPSC interrupt reg.
> Maybe it would be better to make a new property for this but it was only
> one reg and block-index was already there and basically served that
> purpose so I used it.  I'd be happy to use an alternative if you have
> something you think is better.

No, that's an acceptable use for something like this, except that
"cell-index" seems to be the name we've standardised on for other
similar cases.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

Re: [PATCH 1/5] PowerPC 74xx: Katana Qp device tree

[Mark A. Greer]

On Tue, Dec 04, 2007 at 01:50:32PM +1100, David Gibson wrote:
> On Mon, Dec 03, 2007 at 07:10:26PM -0700, Mark A. Greer wrote:
> > On Mon, Dec 03, 2007 at 12:50:18PM +1100, David Gibson wrote:
> > > On Thu, Nov 29, 2007 at 06:28:36PM +0300, Andrei Dolnikov wrote:

> > > > +			eth0 {
> > > > +				device_type = "network";
> > > > +				compatible = "marvell,mv64x60-eth";
> > > > +				block-index = <0>;
> > > 
> > > This block-index thing is crap.  If you really need to subindex nodes
> > > like this, use "reg", with an appropriate #address-cells in the
> > > parent, then the nodes will also get sensible unit addresses.
> > 
> > So how would that work for the "PHY Address Register 0x2000", say,
> > where bits 0-4 set the device addr for PHY 0; bits 5-9 set the device
> > addr for PHY 1; bts 10-14 set the devce addr for PHY 2?
> 
> So use 'reg' to do the indexing.  As long as you have no 'ranges'
> property in the parent 'ethernet' node, which you don't, you can use
> 'reg' as a private index.  That's basically what non-translatable reg
> values are about.
> 
> Incidentally you should probably call the subnodes "ethernet@0"
> etc. and the parent one "multiethernet" or something.  It's the
> subnodes that represent an individual ethernet interface, so they
> should take the "ethernet" name and not the parent, by generic names
> conventions.

Okay, thanks for the advice.  I'll fix the prpmc2800 dts file.
Presumably Andrei will fix his.

> [snip]
> > > > +		sdma@4000 {
> > > > +			compatible = "marvell,mv64x60-sdma";
> > > > +			reg = <4000 c18>;
> > > > +			virtual-reg = <f8104000>;
> > > 
> > > Why does this node have virtual-reg?
> > 
> > "virtual-reg" is a special property that doesn't get translated thru
> > the parent mappings.  It should never be used in the kernel.  Its
> > purpose is to give code in the bootwrapper the exact address that it
> > should use to access a register or block of registers or ...
> > Its needed here because the MPSC (serial) driver uses the SDMA unit
> > to perform console I/O in the bootwrapper (e.g., cmdline editing, printf's).
> > 
> > Yes, this needs to be documented.
> 
> Ok.  "it's used for serial in the bootwrapper" would have sufficed - I
> questioned it because it wasn't obvious that this was needed to use
> the mpsc.

Sorry  :)

> > 
> > > > +		mpsc@8000 {
> > > > +			device_type = "serial";
> > > > +			compatible = "marvell,mpsc";
> > > > +			reg = <8000 38>;
> > > > +			virtual-reg = <f8108000>;
> > > > +			sdma = <&/mv64x60/sdma@4000>;
> > > > +			brg = <&/mv64x60/brg@b200>;
> > > > +			cunit = <&/mv64x60/cunit@f200>;
> > > > +			mpscrouting = <&/mv64x60/mpscrouting@b400>;
> > > > +			mpscintr = <&/mv64x60/mpscintr@b800>;
> > > > +			block-index = <0>;
> > > 
> > > What is this block-index thing about here?  Since the devices are
> > > disambiguated by their register address, why do you need it?
> > 
> > This particular one is needed to access the correct MPSC interrupt reg.
> > Maybe it would be better to make a new property for this but it was only
> > one reg and block-index was already there and basically served that
> > purpose so I used it.  I'd be happy to use an alternative if you have
> > something you think is better.
> 
> No, that's an acceptable use for something like this, except that
> "cell-index" seems to be the name we've standardised on for other
> similar cases.

Yeah, I realize that but block-index was here first!
More seriously, I don't like "cell" because it isn't a cell, its a
block or an instance or an...I dunno but its not a cell IMHO.
Anyway, I'll think about changing it to cell but I already feel
dirty just thinking about it.

Mark

Re: [PATCH 1/5] PowerPC 74xx: Katana Qp device tree

[Mark A. Greer]

On Tue, Dec 04, 2007 at 01:14:43PM +1100, Benjamin Herrenschmidt wrote:
> 
>  .../... (snip scary bunch of errata)
> 
> > - "FEr PCI-#4" (Detailed by Application Note AN-84):
> > 
> > [This isn't strictly a coherency issue but having coherency enabled
> > exacerbates the problem.]  Basically, the bridge can let the cpu read
> > a pci device's registers before all of the data the PCI devices has
> > written has actually made it to memory.  This and the fact that the
> > device's write data may be stuck in the PCI Slave Write Buffer
> > (which isn't checked for coherency), the cpu can get stale data.
> > 
> > There are no plans to fix that erratum.
> 
> So if I understand correctly, there's no plan to fix a major PCI spec
> violation which prevent any kind of reliable implementation whatsoever ?

That's just for that particular part (e.g., 64360).  Newer parts like
the 64460 have it fixed.

> > So, the answer depends on what part & what rev of the part you have
> > (e.g., the pegasos doesn't use the MPSC and apparently has the other
> > issues worked around so it can turn on coherency but the prpmc2800
> > doesn't so it needs coherency off).
> > 
> > BTW, I haven't forgotten the inherent bug you described when coherency
> > is off (/me too lazy to find link to the email) but AFAIK I've never run
> > into it.  However, if I turn on coherency and stress the PCI bus, it
> > hangs (I can't even look at memory thru a bdi).
> 
> Well, as it is today, the "classic" MMU code cannot deal with !coherent.
> The entire linear mapping is always mapped cacheable with BATs, so stuff
> may be brought into the cache at any time, potentially polluting DMA
> data.
>
> Dealing with that would be hard. It might be possible by using G on the
> entire linear mapping like we do on 4xx (yuck), and/or by not using
> D-BATs (the kernel will blow up in various areas without I-BATs).

Hrm, I didn't realize it was in such bad shape.  I'll have to take a
closer look.

Mark

Re: [PATCH 1/5] PowerPC 74xx: Katana Qp device tree

[Jon Loeliger]

David Gibson wrote:
> On Mon, Dec 03, 2007 at 01:26:34PM -0600, Jon Loeliger wrote:
>> On Sun, 2007-12-02 at 19:50, David Gibson wrote:
>>
>>>> +		clock-frequency = <7f28155>;		/* 133.333333 MHz */
>>> You can use <d# 133333333> to avoid the ugly hex.
>> Better still, blaze a new trail, convert it to /dts-v1/ and
>> use clock-frequency = <133333333> straight up!
> 
> Hrm.. probably best to wait for dtc to go into the kernel for that.
> 

I disagree.

jdl

Re: [PATCH 1/5] PowerPC 74xx: Katana Qp device tree

[Andrei Dolnikov]

Mark A. Greer wrote:
> On Tue, Dec 04, 2007 at 07:52:50AM +1100, Benjamin Herrenschmidt wrote:
>   
>>> 	#address-cells = <1>;
>>> +	#size-cells = <1>;
>>> +	model = "Katana-Qp"; /* Default */
>>> +	compatible = "emerson,Katana-Qp";
>>> +	coherency-off;
>>> +
>>>       
>> What do that mean (coherency-off) ?
>>
>> Somebody is trying again to use a 74xx with non cache coherent DMA ?
>>     
>
> Hi Ben.
>
> I suspect Andrei got that from the prpmc2800 dts which I made so I'll
> jump in.  (BTW, this is the same debate we have every year or two. :)
>
> By looking at the dts, that board has an mv64460 which has a couple
> issues when it comes to coherency (depending on the rev of the chip).
>
> One is about not being able to use DCBST instructions with coherency on
> and the other is about limiting the length of one of the traces (which
> at least one board manufacturer that I know of refuses to implement).
> The first one is supposed to be fixed by rev A1 of the part and the second
> is supposed to be fixed by rev B0 of the part.  I don't know what rev(s)
> are on the board(s) Andrei is using.  If its B0 or later, in theory, the
> part should work with coherency on.
>
> Andrei, have you tested with coherency on?
>   
Yes, I tested it with "coherency on", but it didn't work.

I checked chip revisions on all boards I have and they all are >= 
mv64_4_60 B0.
Emerson team working on U-Boot for KatanaQP (David Jenkins copied in cc) 
notified that they have newer firmware version which makes "coherency 
on" functional.
At the moment I have no more details on it, but I'll investigate this 
issue soon and let you know all the details.
> --
> [snip errata]
> --
>
> So, the answer depends on what part & what rev of the part you have
> (e.g., the pegasos doesn't use the MPSC and apparently has the other
> issues worked around so it can turn on coherency but the prpmc2800
> doesn't so it needs coherency off).
>
> BTW, I haven't forgotten the inherent bug you described when coherency
> is off (/me too lazy to find link to the email) but AFAIK I've never run
> into it.  However, if I turn on coherency and stress the PCI bus, it
> hangs (I can't even look at memory thru a bdi).
>
> Mark
>   
Thanks,
Andrei.

Re: [PATCH 1/5] PowerPC 74xx: Katana Qp device tree

[Mark A. Greer]

On Tue, Dec 04, 2007 at 08:28:57PM +0300, Andrei Dolnikov wrote:
> Mark A. Greer wrote:
> >On Tue, Dec 04, 2007 at 07:52:50AM +1100, Benjamin Herrenschmidt wrote:
> >  
> >>>	#address-cells = <1>;
> >>>+	#size-cells = <1>;
> >>>+	model = "Katana-Qp"; /* Default */
> >>>+	compatible = "emerson,Katana-Qp";
> >>>+	coherency-off;
> >>>+
> >>>      
> >>What do that mean (coherency-off) ?
> >>
> >>Somebody is trying again to use a 74xx with non cache coherent DMA ?
> >>    
> >
> >Hi Ben.
> >
> >I suspect Andrei got that from the prpmc2800 dts which I made so I'll
> >jump in.  (BTW, this is the same debate we have every year or two. :)
> >
> >By looking at the dts, that board has an mv64460 which has a couple
> >issues when it comes to coherency (depending on the rev of the chip).
> >
> >One is about not being able to use DCBST instructions with coherency on
> >and the other is about limiting the length of one of the traces (which
> >at least one board manufacturer that I know of refuses to implement).
> >The first one is supposed to be fixed by rev A1 of the part and the second
> >is supposed to be fixed by rev B0 of the part.  I don't know what rev(s)
> >are on the board(s) Andrei is using.  If its B0 or later, in theory, the
> >part should work with coherency on.
> >
> >Andrei, have you tested with coherency on?
> >  
> Yes, I tested it with "coherency on", but it didn't work.
> 
> I checked chip revisions on all boards I have and they all are >= 
> mv64_4_60 B0.

FWIW, this is consistent with what I see.

Mark

Re: [PATCH 1/5] PowerPC 74xx: Katana Qp device tree

[Mark A. Greer]

David, et. al.,

This is a big blob patch of what I've changed for the prpmc2800.  It
includes the necessary changes in the kernel which you can probably
ignore but they're there for reference.  If you like the dts, then I'll
split the blob up into logical pieces and Andrei can make similar
changes for the Katana Qp.

Let me know what you think.

Mark
---
This patch is based on the latest powerpc.git tree
(44032af0e7d5467b12f998dbf2f1cd23c5324fd5) with the following patches
applied:

http://patchwork.ozlabs.org/linuxppc/patch?id=14339
http://patchwork.ozlabs.org/linuxppc/patch?id=14397
http://patchwork.ozlabs.org/linuxppc/patch?id=14396
http://patchwork.ozlabs.org/linuxppc/patch?id=14631
http://patchwork.ozlabs.org/linuxppc/patch?id=14632
http://patchwork.ozlabs.org/linuxppc/patch?id=14633
http://patchwork.ozlabs.org/linuxppc/patch?id=15007

 arch/powerpc/boot/dts/prpmc2800.dts            |  320 +++++++--------
 arch/powerpc/boot/mpsc.c                       |    2 
 arch/powerpc/boot/serial.c                     |    2 
 arch/powerpc/platforms/embedded6xx/prpmc2800.c |    4 
 arch/powerpc/sysdev/mv64x60_dev.c              |   29 -
 arch/powerpc/sysdev/mv64x60_pci.c              |    6 
 arch/powerpc/sysdev/mv64x60_pic.c              |    4 
 arch/powerpc/sysdev/mv64x60_udbg.c             |    4 
 8 files changed, 181 insertions(+), 190 deletions(-)


diff --git a/arch/powerpc/boot/dts/prpmc2800.dts b/arch/powerpc/boot/dts/prpmc2800.dts
index 24944ca..080130e 100644
--- a/arch/powerpc/boot/dts/prpmc2800.dts
+++ b/arch/powerpc/boot/dts/prpmc2800.dts
@@ -11,6 +11,8 @@
  * if it can determine the exact PrPMC type.
  */
 
+/dts-v1/;
+
 / {
 	#address-cells = <1>;
 	#size-cells = <1>;
@@ -25,64 +27,64 @@
 		PowerPC,7447 {
 			device_type = "cpu";
 			reg = <0>;
-			clock-frequency = <2bb0b140>;	/* Default (733 MHz) */
-			bus-frequency = <7f28155>;	/* 133.333333 MHz */
-			timebase-frequency = <1fca055>;	/* 33.333333 MHz */
-			i-cache-line-size = <20>;
-			d-cache-line-size = <20>;
-			i-cache-size = <8000>;
-			d-cache-size = <8000>;
+			clock-frequency = <733333333>;	/* Default */
+			bus-frequency = <133333333>;
+			timebase-frequency = <33333333>;
+			i-cache-line-size = <0x20>;
+			d-cache-line-size = <0x20>;
+			i-cache-size = <0x8000>;
+			d-cache-size = <0x8000>;
 		};
 	};
 
 	memory {
 		device_type = "memory";
-		reg = <00000000 20000000>;	/* Default (512MB) */
+		reg = <0x00000000 0x20000000>;	/* Default (512MB) */
 	};
 
 	mv64x60@f1000000 { /* Marvell Discovery */
 		#address-cells = <1>;
 		#size-cells = <1>;
 		model = "mv64360";			/* Default */
-		compatible = "marvell,mv64x60";
-		clock-frequency = <7f28155>;		/* 133.333333 MHz */
-		reg = <f1000000 00010000>;
-		virtual-reg = <f1000000>;
-		ranges = <88000000 88000000 01000000	/* PCI 0 I/O Space */
-			  80000000 80000000 08000000	/* PCI 0 MEM Space */
-			  a0000000 a0000000 04000000	/* User FLASH */
-			  00000000 f1000000 00010000	/* Bridge's regs */
-			  f2000000 f2000000 00040000>;	/* Integrated SRAM */
+		compatible = "marvell,mv64360";
+		clock-frequency = <133333333>;
+		reg = <0xf1000000 0x00010000>;
+		virtual-reg = <0xf1000000>;
+		ranges = <0x88000000 0x88000000 0x01000000 /* PCI 0 I/O Space */
+			  0x80000000 0x80000000 0x08000000 /* PCI 0 MEM Space */
+			  0xa0000000 0xa0000000 0x04000000 /* User FLASH */
+			  0x00000000 0xf1000000 0x00010000 /* Bridge's regs */
+			  0xf2000000 0xf2000000 0x00040000>;/* Integrated SRAM*/
 
 		flash@a0000000 {
 			compatible = "cfi-flash";
-			reg = <a0000000 04000000>;
+			reg = <0xa0000000 0x04000000>;
 			bank-width = <4>;
 			device-width = <2>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			fw@0 {
 				label = "FW Image A";
-				reg = <00000000 00100000>;
+				reg = <0x00000000 0x00100000>;
 				read-only;
 			};
 			cfg@100000 {
 				label = "FW Config Data";	/* RW */
-				reg = <00100000 00040000>;
+				reg = <0x00100000 0x00040000>;
 			};
 			kernel@140000 {
 				label = "Kernel Image";
-				reg = <00140000 00400000>;
+				reg = <0x00140000 0x00400000>;
 				read-only;
 			};
 			fs@540000 {
 				label = "Filesystem";
-				reg = <00540000 039c0000>;
+				reg = <0x00540000 0x039c0000>;
 				read-only;
 			};
 			fw@3f00000 {
 				label = "FW Image B";
-				reg = <03f00000 00100000>;
+				reg = <0x03f00000 0x00100000>;
 				read-only;
 			};
 		};
@@ -91,171 +93,167 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			device_type = "mdio";
-			compatible = "marvell,mv64x60-mdio";
-			ethernet-phy@1 {
+			compatible = "marvell,mv64360-mdio";
+			phy0: ethernet-phy@1 {
 				device_type = "ethernet-phy";
 				compatible = "broadcom,bcm5421";
-				interrupts = <4c>;	/* GPP 12 */
-				interrupt-parent = <&/mv64x60/pic>;
+				interrupts = <76>;	/* GPP 12 */
+				interrupt-parent = <&pic>;
 				reg = <1>;
 			};
-			ethernet-phy@3 {
+			phy1: ethernet-phy@3 {
 				device_type = "ethernet-phy";
 				compatible = "broadcom,bcm5421";
-				interrupts = <4c>;	/* GPP 12 */
-				interrupt-parent = <&/mv64x60/pic>;
+				interrupts = <76>;	/* GPP 12 */
+				interrupt-parent = <&pic>;
 				reg = <3>;
 			};
 		};
 
-		ethernet@2000 {
-			reg = <2000 2000>;
-			eth0 {
+		multiethernet@2000 {
+			reg = <0x2000 0x2000>;
+			ethernet@0 {
 				device_type = "network";
-				compatible = "marvell,mv64x60-eth";
-				block-index = <0>;
-				interrupts = <20>;
-				interrupt-parent = <&/mv64x60/pic>;
-				phy = <&/mv64x60/mdio/ethernet-phy@1>;
+				compatible = "marvell,mv64360-eth";
+				reg = <0>;
+				interrupts = <32>;
+				interrupt-parent = <&pic>;
+				phy = <&phy0>;
 				local-mac-address = [ 00 00 00 00 00 00 ];
 			};
-			eth1 {
+			ethernet@1 {
 				device_type = "network";
-				compatible = "marvell,mv64x60-eth";
-				block-index = <1>;
-				interrupts = <21>;
-				interrupt-parent = <&/mv64x60/pic>;
-				phy = <&/mv64x60/mdio/ethernet-phy@3>;
+				compatible = "marvell,mv64360-eth";
+				reg = <1>;
+				interrupts = <33>;
+				interrupt-parent = <&pic>;
+				phy = <&phy1>;
 				local-mac-address = [ 00 00 00 00 00 00 ];
 			};
 		};
 
-		sdma@4000 {
-			device_type = "dma";
-			compatible = "marvell,mv64x60-sdma";
-			reg = <4000 c18>;
-			virtual-reg = <f1004000>;
+		sdma0: sdma@4000 {
+			compatible = "marvell,mv64360-sdma";
+			reg = <0x4000 0xc18>;
+			virtual-reg = <0xf1004000>;
 			interrupt-base = <0>;
-			interrupts = <24>;
-			interrupt-parent = <&/mv64x60/pic>;
+			interrupts = <36>;
+			interrupt-parent = <&pic>;
 		};
 
-		sdma@6000 {
-			device_type = "dma";
-			compatible = "marvell,mv64x60-sdma";
-			reg = <6000 c18>;
-			virtual-reg = <f1006000>;
+		sdma1: sdma@6000 {
+			compatible = "marvell,mv64360-sdma";
+			reg = <0x6000 0xc18>;
+			virtual-reg = <0xf1006000>;
 			interrupt-base = <0>;
-			interrupts = <26>;
-			interrupt-parent = <&/mv64x60/pic>;
+			interrupts = <38>;
+			interrupt-parent = <&pic>;
 		};
 
-		brg@b200 {
-			compatible = "marvell,mv64x60-brg";
-			reg = <b200 8>;
+		brg0: brg@b200 {
+			compatible = "marvell,mv64360-brg";
+			reg = <0xb200 0x8>;
 			clock-src = <8>;
-			clock-frequency = <7ed6b40>;
-			current-speed = <2580>;
+			clock-frequency = <133000000>;
+			current-speed = <9600>;
 			bcr = <0>;
 		};
 
-		brg@b208 {
-			compatible = "marvell,mv64x60-brg";
-			reg = <b208 8>;
+		brg1: brg@b208 {
+			compatible = "marvell,mv64360-brg";
+			reg = <0xb208 0x8>;
 			clock-src = <8>;
-			clock-frequency = <7ed6b40>;
-			current-speed = <2580>;
+			clock-frequency = <133000000>;
+			current-speed = <9600>;
 			bcr = <0>;
 		};
 
-		cunit@f200 {
-			reg = <f200 200>;
+		cunit: cunit@f200 {
+			reg = <0xf200 0x200>;
 		};
 
-		mpscrouting@b400 {
-			reg = <b400 c>;
+		mpscrouting: mpscrouting@b400 {
+			reg = <0xb400 0xc>;
 		};
 
-		mpscintr@b800 {
-			reg = <b800 100>;
-			virtual-reg = <f100b800>;
+		mpscintr: mpscintr@b800 {
+			reg = <0xb800 0x100>;
+			virtual-reg = <0xf100b800>;
 		};
 
-		mpsc@8000 {
+		mpsc0: mpsc@8000 {
 			device_type = "serial";
-			compatible = "marvell,mpsc";
-			reg = <8000 38>;
-			virtual-reg = <f1008000>;
-			sdma = <&/mv64x60/sdma@4000>;
-			brg = <&/mv64x60/brg@b200>;
-			cunit = <&/mv64x60/cunit@f200>;
-			mpscrouting = <&/mv64x60/mpscrouting@b400>;
-			mpscintr = <&/mv64x60/mpscintr@b800>;
-			block-index = <0>;
-			max_idle = <28>;
+			compatible = "marvell,mv64360-mpsc";
+			reg = <0x8000 0x38>;
+			virtual-reg = <0xf1008000>;
+			sdma = <&sdma0>;
+			brg = <&brg0>;
+			cunit = <&cunit>;
+			mpscrouting = <&mpscrouting>;
+			mpscintr = <&mpscintr>;
+			cell-index = <0>;
+			max_idle = <40>;
 			chr_1 = <0>;
 			chr_2 = <0>;
 			chr_10 = <3>;
 			mpcr = <0>;
-			interrupts = <28>;
-			interrupt-parent = <&/mv64x60/pic>;
+			interrupts = <40>;
+			interrupt-parent = <&pic>;
 		};
 
-		mpsc@9000 {
+		mpsc1: mpsc@9000 {
 			device_type = "serial";
-			compatible = "marvell,mpsc";
-			reg = <9000 38>;
-			virtual-reg = <f1009000>;
-			sdma = <&/mv64x60/sdma@6000>;
-			brg = <&/mv64x60/brg@b208>;
-			cunit = <&/mv64x60/cunit@f200>;
-			mpscrouting = <&/mv64x60/mpscrouting@b400>;
-			mpscintr = <&/mv64x60/mpscintr@b800>;
-			block-index = <1>;
-			max_idle = <28>;
+			compatible = "marvell,mv64360-mpsc";
+			reg = <0x9000 0x38>;
+			virtual-reg = <0xf1009000>;
+			sdma = <&sdma1>;
+			brg = <&brg1>;
+			cunit = <&cunit>;
+			mpscrouting = <&mpscrouting>;
+			mpscintr = <&mpscintr>;
+			cell-index = <1>;
+			max_idle = <40>;
 			chr_1 = <0>;
 			chr_2 = <0>;
 			chr_10 = <3>;
 			mpcr = <0>;
-			interrupts = <2a>;
-			interrupt-parent = <&/mv64x60/pic>;
+			interrupts = <42>;
+			interrupt-parent = <&pic>;
 		};
 
 		wdt@b410 {			/* watchdog timer */
-			compatible = "marvell,mv64x60-wdt";
-			reg = <b410 8>;
-			timeout = <a>;		/* wdt timeout in seconds */
+			compatible = "marvell,mv64360-wdt";
+			reg = <0xb410 0x8>;
 		};
 
 		i2c@c000 {
 			device_type = "i2c";
-			compatible = "marvell,mv64x60-i2c";
-			reg = <c000 20>;
-			virtual-reg = <f100c000>;
+			compatible = "marvell,mv64360-i2c";
+			reg = <0xc000 0x20>;
+			virtual-reg = <0xf100c000>;
 			freq_m = <8>;
 			freq_n = <3>;
-			timeout = <3e8>;		/* 1000 = 1 second */
 			retries = <1>;
-			interrupts = <25>;
-			interrupt-parent = <&/mv64x60/pic>;
+			interrupts = <37>;
+			interrupt-parent = <&pic>;
 		};
 
-		pic {
+		pic: pic@0 {
 			#interrupt-cells = <1>;
 			#address-cells = <0>;
-			compatible = "marvell,mv64x60-pic";
-			reg = <0000 88>;
+			compatible = "marvell,mv64360-pic";
+			reg = <0x0000 0x88>;
 			interrupt-controller;
 		};
 
 		mpp@f000 {
-			compatible = "marvell,mv64x60-mpp";
-			reg = <f000 10>;
+			compatible = "marvell,mv64360-mpp";
+			reg = <0xf000 0x10>;
 		};
 
 		gpp@f100 {
-			compatible = "marvell,mv64x60-gpp";
-			reg = <f100 20>;
+			compatible = "marvell,mv64360-gpp";
+			reg = <0xf100 0x20>;
 		};
 
 		pci@80000000 {
@@ -263,68 +261,70 @@
 			#size-cells = <2>;
 			#interrupt-cells = <1>;
 			device_type = "pci";
-			compatible = "marvell,mv64x60-pci";
-			reg = <0cf8 8>;
-			ranges = <01000000 0        0 88000000 0 01000000
-				  02000000 0 80000000 80000000 0 08000000>;
-			bus-range = <0 ff>;
-			clock-frequency = <3EF1480>;
-			interrupt-pci-iack = <0c34>;
-			interrupt-parent = <&/mv64x60/pic>;
-			interrupt-map-mask = <f800 0 0 7>;
+			compatible = "marvell,mv64360-pci";
+			reg = <0x0cf8 0x8>;
+			ranges = <0x01000000 0x0        0x0
+					0x88000000 0x0 0x01000000
+				  0x02000000 0x0 0x80000000
+					0x80000000 0x0 0x08000000>;
+			bus-range = <0x0 0xff>;
+			clock-frequency = <66000000>;
+			interrupt-pci-iack = <0x0c34>;
+			interrupt-parent = <&pic>;
+			interrupt-map-mask = <0xf800 0 0 7>;
 			interrupt-map = <
 				/* IDSEL 0x0a */
-				5000 0 0 1 &/mv64x60/pic 50
-				5000 0 0 2 &/mv64x60/pic 51
-				5000 0 0 3 &/mv64x60/pic 5b
-				5000 0 0 4 &/mv64x60/pic 5d
+				0x5000 0 0 1 &pic 80
+				0x5000 0 0 2 &pic 81
+				0x5000 0 0 3 &pic 91
+				0x5000 0 0 4 &pic 93
 
 				/* IDSEL 0x0b */
-				5800 0 0 1 &/mv64x60/pic 5b
-				5800 0 0 2 &/mv64x60/pic 5d
-				5800 0 0 3 &/mv64x60/pic 50
-				5800 0 0 4 &/mv64x60/pic 51
+				0x5800 0 0 1 &pic 91
+				0x5800 0 0 2 &pic 93
+				0x5800 0 0 3 &pic 80
+				0x5800 0 0 4 &pic 81
 
 				/* IDSEL 0x0c */
-				6000 0 0 1 &/mv64x60/pic 5b
-				6000 0 0 2 &/mv64x60/pic 5d
-				6000 0 0 3 &/mv64x60/pic 50
-				6000 0 0 4 &/mv64x60/pic 51
+				0x6000 0 0 1 &pic 91
+				0x6000 0 0 2 &pic 93
+				0x6000 0 0 3 &pic 80
+				0x6000 0 0 4 &pic 81
 
 				/* IDSEL 0x0d */
-				6800 0 0 1 &/mv64x60/pic 5d
-				6800 0 0 2 &/mv64x60/pic 50
-				6800 0 0 3 &/mv64x60/pic 51
-				6800 0 0 4 &/mv64x60/pic 5b
+				0x6800 0 0 1 &pic 93
+				0x6800 0 0 2 &pic 80
+				0x6800 0 0 3 &pic 81
+				0x6800 0 0 4 &pic 91
 			>;
 		};
 
-		cpu-error@0070 {
-			compatible = "marvell,mv64x60-cpu-error";
-			reg = <0070 10 0128 28>;
-			interrupts = <03>;
-			interrupt-parent = <&/mv64x60/pic>;
+		cpu-error@70 {
+			compatible = "marvell,mv64360-cpu-error";
+			reg = <0x0070 0x10 0x0128 0x28>;
+			interrupts = <3>;
+			interrupt-parent = <&pic>;
 		};
 
-		sram-ctrl@0380 {
-			compatible = "marvell,mv64x60-sram-ctrl";
-			reg = <0380 80>;
-			interrupts = <0d>;
-			interrupt-parent = <&/mv64x60/pic>;
+		sram-ctrl@380 {
+			compatible = "marvell,mv64360-sram-ctrl";
+			reg = <0x0380 0x80>;
+			interrupts = <13>;
+			interrupt-parent = <&pic>;
 		};
 
 		pci-error@1d40 {
-			compatible = "marvell,mv64x60-pci-error";
-			reg = <1d40 40 0c28 4>;
-			interrupts = <0c>;
-			interrupt-parent = <&/mv64x60/pic>;
+			compatible = "marvell,mv64360-pci-error";
+			reg = <0x1d40 0x40 0x0c28 0x4>;
+			interrupts = <12>;
+			interrupt-parent = <&pic>;
 		};
 
 		mem-ctrl@1400 {
-			compatible = "marvell,mv64x60-mem-ctrl";
-			reg = <1400 60>;
-			interrupts = <11>;
-			interrupt-parent = <&/mv64x60/pic>;
+			compatible = "marvell,mv64360-mem-ctrl";
+			reg = <0x1400 0x60>;
+			interrupts = <17>;
+			interrupt-parent = <&pic>;
 		};
 	};
 
diff --git a/arch/powerpc/boot/mpsc.c b/arch/powerpc/boot/mpsc.c
index 802ea53..425ad88 100644
--- a/arch/powerpc/boot/mpsc.c
+++ b/arch/powerpc/boot/mpsc.c
@@ -141,7 +141,7 @@ int mpsc_console_init(void *devp, struct serial_console_data *scdp)
 	if (mpscintr_base == NULL)
 		goto err_out;
 
-	n = getprop(devp, "block-index", &v, sizeof(v));
+	n = getprop(devp, "cell-index", &v, sizeof(v));
 	if (n != sizeof(v))
 		goto err_out;
 	reg_set = (int)v;
diff --git a/arch/powerpc/boot/serial.c b/arch/powerpc/boot/serial.c
index cafeece..cbcbb20 100644
--- a/arch/powerpc/boot/serial.c
+++ b/arch/powerpc/boot/serial.c
@@ -119,7 +119,7 @@ int serial_console_init(void)
 
 	if (dt_is_compatible(devp, "ns16550"))
 		rc = ns16550_console_init(devp, &serial_cd);
-	else if (dt_is_compatible(devp, "marvell,mpsc"))
+	else if (dt_is_compatible(devp, "marvell,mv64360-mpsc"))
 		rc = mpsc_console_init(devp, &serial_cd);
 	else if (dt_is_compatible(devp, "fsl,cpm1-scc-uart") ||
 	         dt_is_compatible(devp, "fsl,cpm1-smc-uart") ||
diff --git a/arch/powerpc/platforms/embedded6xx/prpmc2800.c b/arch/powerpc/platforms/embedded6xx/prpmc2800.c
index a01e219..1a1baf9 100644
--- a/arch/powerpc/platforms/embedded6xx/prpmc2800.c
+++ b/arch/powerpc/platforms/embedded6xx/prpmc2800.c
@@ -50,13 +50,13 @@ static void __init prpmc2800_setup_arch(void)
 	 * ioremap mpp and gpp registers in case they are later
 	 * needed by prpmc2800_reset_board().
 	 */
-	np = of_find_compatible_node(NULL, NULL, "marvell,mv64x60-mpp");
+	np = of_find_compatible_node(NULL, NULL, "marvell,mv64360-mpp");
 	reg = of_get_property(np, "reg", NULL);
 	paddr = of_translate_address(np, reg);
 	of_node_put(np);
 	mv64x60_mpp_reg_base = ioremap(paddr, reg[1]);
 
-	np = of_find_compatible_node(NULL, NULL, "marvell,mv64x60-gpp");
+	np = of_find_compatible_node(NULL, NULL, "marvell,mv64360-gpp");
 	reg = of_get_property(np, "reg", NULL);
 	paddr = of_translate_address(np, reg);
 	of_node_put(np);
diff --git a/arch/powerpc/sysdev/mv64x60_dev.c b/arch/powerpc/sysdev/mv64x60_dev.c
index 304056c..aac28ee 100644
--- a/arch/powerpc/sysdev/mv64x60_dev.c
+++ b/arch/powerpc/sysdev/mv64x60_dev.c
@@ -127,7 +127,7 @@ static int __init mv64x60_mpsc_device_setup(struct device_node *np, int id)
 	if (err)
 		return err;
 
-	prop = of_get_property(np, "block-index", NULL);
+	prop = of_get_property(np, "cell-index", NULL);
 	if (!prop)
 		return -ENODEV;
 	port_number = *(int *)prop;
@@ -248,7 +248,7 @@ static int __init mv64x60_eth_device_setup(struct device_node *np, int id)
 
 	memset(&pdata, 0, sizeof(pdata));
 
-	prop = of_get_property(np, "block-index", NULL);
+	prop = of_get_property(np, "reg", NULL);
 	if (!prop)
 		return -ENODEV;
 	pdata.port_number = *prop;
@@ -344,6 +344,7 @@ static int __init mv64x60_i2c_device_setup(struct device_node *np, int id)
 	of_irq_to_resource(np, 0, &r[1]);
 
 	memset(&pdata, 0, sizeof(pdata));
+	pdata.timeout = 1000;	/* Default: 1 second */
 
 	prop = of_get_property(np, "freq_m", NULL);
 	if (!prop)
@@ -355,12 +356,6 @@ static int __init mv64x60_i2c_device_setup(struct device_node *np, int id)
 		return -ENODEV;
 	pdata.freq_n = *prop;
 
-	prop = of_get_property(np, "timeout", NULL);
-	if (prop)
-		pdata.timeout = *prop;
-	else
-		pdata.timeout = 1000;	/* 1 second */
-
 	prop = of_get_property(np, "retries", NULL);
 	if (prop)
 		pdata.retries = *prop;
@@ -406,11 +401,7 @@ static int __init mv64x60_wdt_device_setup(struct device_node *np, int id)
 		return err;
 
 	memset(&pdata, 0, sizeof(pdata));
-
-	prop = of_get_property(np, "timeout", NULL);
-	if (!prop)
-		return -ENODEV;
-	pdata.timeout = *prop;
+	pdata.timeout = 10;	/* Default: 10 seconds */
 
 	np = of_get_parent(np);
 	if (!np)
@@ -452,22 +443,22 @@ static int __init mv64x60_device_setup(void)
 	int err;
 
 	id = 0;
-	for_each_compatible_node(np, "serial", "marvell,mpsc")
+	for_each_compatible_node(np, "serial", "marvell,mv64360-mpsc")
 		if ((err = mv64x60_mpsc_device_setup(np, id++)))
 			goto error;
 
 	id = 0;
-	for_each_compatible_node(np, "network", "marvell,mv64x60-eth")
+	for_each_compatible_node(np, "network", "marvell,mv64360-eth")
 		if ((err = mv64x60_eth_device_setup(np, id++)))
 			goto error;
 
 	id = 0;
-	for_each_compatible_node(np, "i2c", "marvell,mv64x60-i2c")
+	for_each_compatible_node(np, "i2c", "marvell,mv64360-i2c")
 		if ((err = mv64x60_i2c_device_setup(np, id++)))
 			goto error;
 
 	/* support up to one watchdog timer */
-	np = of_find_compatible_node(np, NULL, "marvell,mv64x60-wdt");
+	np = of_find_compatible_node(np, NULL, "marvell,mv64360-wdt");
 	if (np) {
 		if ((err = mv64x60_wdt_device_setup(np, id)))
 			goto error;
@@ -495,10 +486,10 @@ static int __init mv64x60_add_mpsc_console(void)
 	if (!np)
 		goto not_mpsc;
 
-	if (!of_device_is_compatible(np, "marvell,mpsc"))
+	if (!of_device_is_compatible(np, "marvell,mv64360-mpsc"))
 		goto not_mpsc;
 
-	prop = of_get_property(np, "block-index", NULL);
+	prop = of_get_property(np, "cell-index", NULL);
 	if (!prop)
 		goto not_mpsc;
 
diff --git a/arch/powerpc/sysdev/mv64x60_pci.c b/arch/powerpc/sysdev/mv64x60_pci.c
index d21ab8f..1456015 100644
--- a/arch/powerpc/sysdev/mv64x60_pci.c
+++ b/arch/powerpc/sysdev/mv64x60_pci.c
@@ -86,14 +86,14 @@ static int __init mv64x60_sysfs_init(void)
 	struct platform_device *pdev;
 	const unsigned int *prop;
 
-	np = of_find_compatible_node(NULL, NULL, "marvell,mv64x60");
+	np = of_find_compatible_node(NULL, NULL, "marvell,mv64360");
 	if (!np)
 		return 0;
 
 	prop = of_get_property(np, "hs_reg_valid", NULL);
 	of_node_put(np);
 
-	pdev = platform_device_register_simple("marvell,mv64x60", 0, NULL, 0);
+	pdev = platform_device_register_simple("marvell,mv64360", 0, NULL, 0);
 	if (IS_ERR(pdev))
 		return PTR_ERR(pdev);
 
@@ -166,6 +166,6 @@ void __init mv64x60_pci_init(void)
 {
 	struct device_node *np;
 
-	for_each_compatible_node(np, "pci", "marvell,mv64x60-pci")
+	for_each_compatible_node(np, "pci", "marvell,mv64360-pci")
 		mv64x60_add_bridge(np);
 }
diff --git a/arch/powerpc/sysdev/mv64x60_pic.c b/arch/powerpc/sysdev/mv64x60_pic.c
index 19e6ef2..2aa4ed0 100644
--- a/arch/powerpc/sysdev/mv64x60_pic.c
+++ b/arch/powerpc/sysdev/mv64x60_pic.c
@@ -238,13 +238,13 @@ void __init mv64x60_init_irq(void)
 	const unsigned int *reg;
 	unsigned long flags;
 
-	np = of_find_compatible_node(NULL, NULL, "marvell,mv64x60-gpp");
+	np = of_find_compatible_node(NULL, NULL, "marvell,mv64360-gpp");
 	reg = of_get_property(np, "reg", &size);
 	paddr = of_translate_address(np, reg);
 	mv64x60_gpp_reg_base = ioremap(paddr, reg[1]);
 	of_node_put(np);
 
-	np = of_find_compatible_node(NULL, NULL, "marvell,mv64x60-pic");
+	np = of_find_compatible_node(NULL, NULL, "marvell,mv64360-pic");
 	reg = of_get_property(np, "reg", &size);
 	paddr = of_translate_address(np, reg);
 	mv64x60_irq_reg_base = ioremap(paddr, reg[1]);
diff --git a/arch/powerpc/sysdev/mv64x60_udbg.c b/arch/powerpc/sysdev/mv64x60_udbg.c
index 35c77c7..2792dc8 100644
--- a/arch/powerpc/sysdev/mv64x60_udbg.c
+++ b/arch/powerpc/sysdev/mv64x60_udbg.c
@@ -85,7 +85,7 @@ static void mv64x60_udbg_init(void)
 	if (!stdout)
 		return;
 
-	for_each_compatible_node(np, "serial", "marvell,mpsc") {
+	for_each_compatible_node(np, "serial", "marvell,mv64360-mpsc") {
 		if (np == stdout)
 			break;
 	}
@@ -94,7 +94,7 @@ static void mv64x60_udbg_init(void)
 	if (!np)
 		return;
 
-	block_index = of_get_property(np, "block-index", NULL);
+	block_index = of_get_property(np, "cell-index", NULL);
 	if (!block_index)
 		goto error;
 

Re: [PATCH 1/5] PowerPC 74xx: Katana Qp device tree

[David Gibson]

On Thu, Dec 06, 2007 at 04:27:56PM -0700, Mark A. Greer wrote:
> David, et. al.,
> 
> This is a big blob patch of what I've changed for the prpmc2800.  It
> includes the necessary changes in the kernel which you can probably
> ignore but they're there for reference.  If you like the dts, then I'll
> split the blob up into logical pieces and Andrei can make similar
> changes for the Katana Qp.
> 
> Let me know what you think.

Looks pretty reasonable.  I would have preferred that labels be
uppercase by convention, to make them easier to pick out by eyeball,
but I think that's a lost cause at this stage.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

Re: [PATCH 1/5] PowerPC 74xx: Katana Qp device tree

[Mark A. Greer]

On Sat, Dec 08, 2007 at 12:33:09PM +1100, David Gibson wrote:
> On Thu, Dec 06, 2007 at 04:27:56PM -0700, Mark A. Greer wrote:
> > David, et. al.,
> > 
> > This is a big blob patch of what I've changed for the prpmc2800.  It
> > includes the necessary changes in the kernel which you can probably
> > ignore but they're there for reference.  If you like the dts, then I'll
> > split the blob up into logical pieces and Andrei can make similar
> > changes for the Katana Qp.
> > 
> > Let me know what you think.
> 
> Looks pretty reasonable.  I would have preferred that labels be
> uppercase by convention, to make them easier to pick out by eyeball,
> but I think that's a lost cause at this stage.

I can do that.  Thanks for the feedback.  I'll break the blob up into
pieces and submit with the labels in uppercase.

Thanks,

Mark

Re: [PATCH 1/5] PowerPC 74xx: Katana Qp device tree

[Dale Farnsworth]

David Gibson wrote:
> On Thu, Nov 29, 2007 at 06:28:36PM +0300, Andrei Dolnikov wrote:
> > Device tree source file for the Emerson Katana Qp board

[snip]

> > +	mv64x60@f8100000 { /* Marvell Discovery */
> > +		#address-cells = <1>;
> > +		#size-cells = <1>;
> > +		model = "mv64460";			/* Default */
> > +		compatible = "marvell,mv64x60";

[snip]

> > +		mdio {
> 
> There must be some way of actuall accessing the mdio bus, so this node
> ought to have a 'reg' property and unit address.

There is no way for the cpu to directly access the mdio bus.  The
mdio bus is internally accessed by the ethernet MAC.  That being the
case, maybe it makes more sense to move the mdio node inside of the
multiethernet node, as follows, but I don't see how we can give it
a reg property or a unit address.

		multiethernet@2000 {
			reg = <0x2000 0x2000>;
			ethernet@0 {
				device_type = "network";
				compatible = "marvell,mv64360-eth";
				reg = <0>;
				interrupts = <32>;
				interrupt-parent = <&PIC>;
				phy = <&PHY0>;
				local-mac-address = [ 00 00 00 00 00 00 ];
			};
			ethernet@1 {
				device_type = "network";
				compatible = "marvell,mv64360-eth";
				reg = <1>;
				interrupts = <33>;
				interrupt-parent = <&PIC>;
				phy = <&PHY1>;
				local-mac-address = [ 00 00 00 00 00 00 ];
			};
			mdio {
				#address-cells = <1>;
				#size-cells = <0>;
				device_type = "mdio";
				compatible = "marvell,mv64360-mdio";
				PHY0: ethernet-phy@1 {
					device_type = "ethernet-phy";
					compatible = "broadcom,bcm5421";
					interrupts = <76>;	/* GPP 12 */
					interrupt-parent = <&PIC>;
					reg = <1>;
				};
				PHY1: ethernet-phy@3 {
					device_type = "ethernet-phy";
					compatible = "broadcom,bcm5421";
					interrupts = <76>;	/* GPP 12 */
					interrupt-parent = <&PIC>;
					reg = <3>;
				};
			};
		};

Look OK?

-Dale

Re: [PATCH 2/5] PowerPC 74xx: Minor updates to MV64x60 boot code

[Mark A. Greer]

On Thu, Nov 29, 2007 at 06:35:55PM +0300, Andrei Dolnikov wrote:

Hi Andrei.  I have a few comments below.

> This patch adds new functionality to MV64x60 boot code. The changes are required
> to access DevCS windows registers and set PCI bus and devfn numbers for MV644x60
> PCI/PCI-X interfaces.
> 
> Signed-off-by: Andrei Dolnikov <adolnikov@ru.mvista.com>
> 
> ---
>  mv64x60.c |   74 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
>  mv64x60.h |   10 ++++++++
>  2 files changed, 84 insertions(+)
> 
> diff --git a/arch/powerpc/boot/mv64x60.c b/arch/powerpc/boot/mv64x60.c
> index d207a0b..787a124 100644
> --- a/arch/powerpc/boot/mv64x60.c
> +++ b/arch/powerpc/boot/mv64x60.c
> @@ -32,6 +32,16 @@
>  #define MV64x60_CPU2MEM_3_BASE			0x0218
>  #define MV64x60_CPU2MEM_3_SIZE			0x0220
>  
> +#define MV64x60_DEV2MEM_WINDOWS			4
> +#define MV64x60_DEV2MEM_0_BASE			0x0028
> +#define MV64x60_DEV2MEM_0_SIZE			0x0030
> +#define MV64x60_DEV2MEM_1_BASE			0x0228
> +#define MV64x60_DEV2MEM_1_SIZE			0x0230
> +#define MV64x60_DEV2MEM_2_BASE			0x0248
> +#define MV64x60_DEV2MEM_2_SIZE			0x0250
> +#define MV64x60_DEV2MEM_3_BASE			0x0038
> +#define MV64x60_DEV2MEM_3_SIZE			0x0040
> +

These aren't device->memory windows, they're CPU->device windows so
they should be named MV64x60_CPU2DEV_xxx to be consistent with the
previously established naming convention.

>  #define MV64x60_ENET2MEM_BAR_ENABLE		0x2290
>  #define MV64x60_ENET2MEM_0_BASE			0x2200
>  #define MV64x60_ENET2MEM_0_SIZE			0x2204
> @@ -219,6 +229,25 @@ static struct mv64x60_mem_win mv64x60_cpu2mem[MV64x60_CPU2MEM_WINDOWS] = {
>  	},
>  };
>  
> +static struct mv64x60_mem_win mv64x60_devcs[MV64x60_DEV2MEM_WINDOWS] = {

Why not call this mv64x60_cpu2dev[]?

<snip>

> @@ -586,6 +645,21 @@ u32 mv64x60_get_mem_size(u8 *bridge_base)
>  	return mem;
>  }
>  
> +/* Read a size of DEV_CS window */
> +u32 mv64x60_get_devcs_size(u8 *bridge_base, u32 devcs)

u32 mv64x60_get_cpu2dev_size(...)

<snip>

> diff --git a/arch/powerpc/boot/mv64x60.h b/arch/powerpc/boot/mv64x60.h
> index d0b29a7..a633d2e 100644
> --- a/arch/powerpc/boot/mv64x60.h
> +++ b/arch/powerpc/boot/mv64x60.h
> @@ -12,6 +12,14 @@
>  
>  #define MV64x60_CPU_BAR_ENABLE			0x0278
>  
> +#define MV64x60_PCI0_MODE			0x0d00
> +#define MV64x60_PCI1_MODE			0x0d80
> +#define MV64x60_PCI0_P2P_CONF			0x1d14
> +#define MV64x60_PCI1_P2P_CONF			0x1d94
> +
> +#define MV64x60_PCI_MODE_MASK			0x00000030
> +#define MV64x60_PCI_CONVENTIONAL_MODE		0x00000000
> +

AFAICS these macros are only used in mv64x60.c so just put them there.
They only need to go in mv64x60.h if they're used in more than one .c
file.

Mark

Re: [PATCH 3/5] PowerPC 74xx: Katana Qp bootwrapper

[Mark A. Greer]

On Thu, Nov 29, 2007 at 06:39:51PM +0300, Andrei Dolnikov wrote:
> Bootwrapper sources for Emerson Katana Qp
> 
> Signed-off-by: Andrei Dolnikov <adolnikov@ru.mvista.com>
> 
> ---
>  Makefile          |    3
>  cuboot-katanaqp.c |  470 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 472 insertions(+), 1 deletion(-)

<snip> 

> diff --git a/arch/powerpc/boot/cuboot-katanaqp.c b/arch/powerpc/boot/cuboot-katanaqp.c
> new file mode 100644
> index 0000000..19ba901
> --- /dev/null
> +++ b/arch/powerpc/boot/cuboot-katanaqp.c
> @@ -0,0 +1,470 @@

<snip>

> +	/* Get the cpu -> pci i/o & mem mappings from the device tree */
> +	devp = finddevice("/mv64x60");
> +	if (devp == NULL)
> +		fatal("Error: Missing /mv64x60 device tree node\n\r");
> +
> +
> +	enables = in_le32((u32 *) (bridge_base + MV64x60_CPU_BAR_ENABLE));
> +	enables |= 0x0007fe00;	/* Disable all cpu->pci windows */
> +	out_le32((u32 *) (bridge_base + MV64x60_CPU_BAR_ENABLE), enables);
> +
> +	for (i = 0; i < 12; i += 6) {
> +		switch (v[i] & 0xff000000) {
> +		case 0x01000000:	/* PCI I/O Space */
> +			tbl = mv64x60_cpu2pci_io;
> +			break;
> +		case 0x02000000:	/* PCI MEM Space */
> +			tbl = mv64x60_cpu2pci_mem;
> +			break;
> +		default:
> +			continue;
> +		}
> +
> +		pci_base_hi = v[i + 1];
> +		pci_base_lo = v[i + 2];
> +		cpu_base = v[i + 3];
> +		size = v[i + 5];
> +
> +		buf[0] = cpu_base;
> +		buf[1] = size;
> +
> +		if (!dt_xlate_addr(devp, buf, sizeof(buf), &cpu_base))
> +			fatal("Error: Can't translate PCI address 0x%x\n\r",
> +			      (u32) cpu_base);
> +
> +		mv64x60_config_cpu2pci_window(bridge_base, 1, pci_base_hi,
> +					      pci_base_lo, cpu_base, size, tbl);
> +	}

Looks like we could factor out some of this code that's the same here
and in prpmc2800.c.  I can do that later, though.

<snip>

> +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
> +		   unsigned long r6, unsigned long r7)
> +{
> +
> +	CUBOOT_INIT();
> +
> +	if (ft_init(_dtb_start, _dtb_end - _dtb_start, 16))
> +		exit();

This should be replaced by fdt_init(dtb) now.

<snip>

Mark

Re: [PATCH 4/5] PowerPC 74xx: Katana Qp base support

[Mark A. Greer]

On Thu, Nov 29, 2007 at 06:42:00PM +0300, Andrei Dolnikov wrote:
> Emerson Katana Qp platform specific code
> 
> Signed-off-by: Andrei Dolnikov <adolnikov@ru.mvista.com>

Acked-by: Mark A. Greer <mgreer@mvista.com>

Re: [PATCH 1/5] PowerPC 74xx: Katana Qp device tree

[David Gibson]

On Mon, Dec 10, 2007 at 02:18:16PM -0700, Dale Farnsworth wrote:
> David Gibson wrote:
> > On Thu, Nov 29, 2007 at 06:28:36PM +0300, Andrei Dolnikov wrote:
> > > Device tree source file for the Emerson Katana Qp board
> 
> [snip]
> 
> > > +	mv64x60@f8100000 { /* Marvell Discovery */
> > > +		#address-cells = <1>;
> > > +		#size-cells = <1>;
> > > +		model = "mv64460";			/* Default */
> > > +		compatible = "marvell,mv64x60";
> 
> [snip]
> 
> > > +		mdio {
> > 
> > There must be some way of actuall accessing the mdio bus, so this node
> > ought to have a 'reg' property and unit address.
> 
> There is no way for the cpu to directly access the mdio bus.  The
> mdio bus is internally accessed by the ethernet MAC.  That being the
> case, maybe it makes more sense to move the mdio node inside of the
> multiethernet node, as follows, but I don't see how we can give it
> a reg property or a unit address.

Ah, I see.  If the mdio interface isn't distinct from the other
pieces, then it probably shouldn't get a device node at all.  Having
an explicit mdio bus with the phys hanging off it is convenient for
hardware which actually works that way, but it doesn't have to be done
like that.

Of course, then the question is where to hang the phy nodes, which
look like they have information you need.  Since you already have a
local addressing scheme for the MACs under the multiethernet, what
probably makes sense would be to hang the phys directly under the
multiethernet, using an encoding scheme for the reg properties so that
the MACs and PHYs aren't confused (say, MACs are 0x0, 0x1, 0x2, PHYs
are 0x80000000, 0x80000001, 0x80000002).

Incidentally, although I suggested it, I'm not all that fond of the
"multiethernet" name, it was just the first thing that occurred to me.

> 
> 		multiethernet@2000 {
> 			reg = <0x2000 0x2000>;
> 			ethernet@0 {
> 				device_type = "network";
> 				compatible = "marvell,mv64360-eth";
> 				reg = <0>;
> 				interrupts = <32>;
> 				interrupt-parent = <&PIC>;
> 				phy = <&PHY0>;
> 				local-mac-address = [ 00 00 00 00 00 00 ];
> 			};
> 			ethernet@1 {
> 				device_type = "network";
> 				compatible = "marvell,mv64360-eth";
> 				reg = <1>;
> 				interrupts = <33>;
> 				interrupt-parent = <&PIC>;
> 				phy = <&PHY1>;
> 				local-mac-address = [ 00 00 00 00 00 00 ];
> 			};
> 			mdio {
> 				#address-cells = <1>;
> 				#size-cells = <0>;
> 				device_type = "mdio";
> 				compatible = "marvell,mv64360-mdio";
> 				PHY0: ethernet-phy@1 {
> 					device_type = "ethernet-phy";
> 					compatible = "broadcom,bcm5421";
> 					interrupts = <76>;	/* GPP 12 */
> 					interrupt-parent = <&PIC>;
> 					reg = <1>;
> 				};
> 				PHY1: ethernet-phy@3 {
> 					device_type = "ethernet-phy";
> 					compatible = "broadcom,bcm5421";
> 					interrupts = <76>;	/* GPP 12 */
> 					interrupt-parent = <&PIC>;
> 					reg = <3>;
> 				};
> 			};
> 		};

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

Re: [PATCH 1/5] PowerPC 74xx: Katana Qp device tree

[Dale Farnsworth]

On Sun, Dec 16, 2007 at 05:40:56PM +1100, David Gibson wrote:
> On Mon, Dec 10, 2007 at 02:18:16PM -0700, Dale Farnsworth wrote:
> > David Gibson wrote:
> > > On Thu, Nov 29, 2007 at 06:28:36PM +0300, Andrei Dolnikov wrote:
> > > > Device tree source file for the Emerson Katana Qp board
> > 
> > [snip]
> > 
> > > > +	mv64x60@f8100000 { /* Marvell Discovery */
> > > > +		#address-cells = <1>;
> > > > +		#size-cells = <1>;
> > > > +		model = "mv64460";			/* Default */
> > > > +		compatible = "marvell,mv64x60";
> > 
> > [snip]
> > 
> > > > +		mdio {
> > > 
> > > There must be some way of actuall accessing the mdio bus, so this node
> > > ought to have a 'reg' property and unit address.
> > 
> > There is no way for the cpu to directly access the mdio bus.  The
> > mdio bus is internally accessed by the ethernet MAC.  That being the
> > case, maybe it makes more sense to move the mdio node inside of the
> > multiethernet node, as follows, but I don't see how we can give it
> > a reg property or a unit address.
> 
> Ah, I see.  If the mdio interface isn't distinct from the other
> pieces, then it probably shouldn't get a device node at all.  Having
> an explicit mdio bus with the phys hanging off it is convenient for
> hardware which actually works that way, but it doesn't have to be done
> like that.
> 
> Of course, then the question is where to hang the phy nodes, which
> look like they have information you need.  Since you already have a
> local addressing scheme for the MACs under the multiethernet, what
> probably makes sense would be to hang the phys directly under the
> multiethernet, using an encoding scheme for the reg properties so that
> the MACs and PHYs aren't confused (say, MACs are 0x0, 0x1, 0x2, PHYs
> are 0x80000000, 0x80000001, 0x80000002).

Ugh.  They really are two separate address spaces.  One is an
intra-register index, and the other really is an mdio address,
even though it's only indirectly addressable.  Combining them would
obfuscate.  I'm proceding with an mdio node under the multiethernet
node as I posted below.  Let me know if you feel strongly that that
should be changed.

> Incidentally, although I suggested it, I'm not all that fond of the
> "multiethernet" name, it was just the first thing that occurred to me.

I'm not fond of it either.  Sometimes, naming is hard. :)
I'll see if we can come up with something better.

Thanks,
-Dale

> > 
> > 		multiethernet@2000 {
> > 			reg = <0x2000 0x2000>;
> > 			ethernet@0 {
> > 				device_type = "network";
> > 				compatible = "marvell,mv64360-eth";
> > 				reg = <0>;
> > 				interrupts = <32>;
> > 				interrupt-parent = <&PIC>;
> > 				phy = <&PHY0>;
> > 				local-mac-address = [ 00 00 00 00 00 00 ];
> > 			};
> > 			ethernet@1 {
> > 				device_type = "network";
> > 				compatible = "marvell,mv64360-eth";
> > 				reg = <1>;
> > 				interrupts = <33>;
> > 				interrupt-parent = <&PIC>;
> > 				phy = <&PHY1>;
> > 				local-mac-address = [ 00 00 00 00 00 00 ];
> > 			};
> > 			mdio {
> > 				#address-cells = <1>;
> > 				#size-cells = <0>;
> > 				device_type = "mdio";
> > 				compatible = "marvell,mv64360-mdio";
> > 				PHY0: ethernet-phy@1 {
> > 					device_type = "ethernet-phy";
> > 					compatible = "broadcom,bcm5421";
> > 					interrupts = <76>;	/* GPP 12 */
> > 					interrupt-parent = <&PIC>;
> > 					reg = <1>;
> > 				};
> > 				PHY1: ethernet-phy@3 {
> > 					device_type = "ethernet-phy";
> > 					compatible = "broadcom,bcm5421";
> > 					interrupts = <76>;	/* GPP 12 */
> > 					interrupt-parent = <&PIC>;
> > 					reg = <3>;
> > 				};
> > 			};
> > 		};