From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from az33egw01.freescale.net (az33egw01.freescale.net [192.88.158.102]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "az33egw01.freescale.net", Issuer "Thawte Premium Server CA" (verified OK)) by ozlabs.org (Postfix) with ESMTP id 13759DDEAB for ; Fri, 25 Jan 2008 07:12:39 +1100 (EST) Date: Thu, 24 Jan 2008 14:12:26 -0600 From: Scott Wood To: Poonam_Aggrwal-b10812 Subject: Re: [PATCH UCC TDM 3/3 ] Modified Documentation to explain dts entries for TDM driver Message-ID: <20080124201226.GA3926@loki.buserror.net> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii In-Reply-To: Cc: michael.barkowski@freescale.com, netdev@vger.kernel.org, kumar.gala@freescale.com, linux-kernel@vger.kernel.org, rubini@vision.unipv.it, linuxppc-dev@ozlabs.org, ashish.kalra@freescale.com, rich.cutler@freescale.com, akpm@linux-foundation.org, timur@freescale.com List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Thu, Jan 24, 2008 at 10:24:13AM +0530, Poonam_Aggrwal-b10812 wrote: > + ix) Baud Rate Generator (BRG) > + > + Required properties: > + - compatible : shpuld be "fsl,cpm-brg" > + - fsl,brg-sources : define the input clock for all 16 BRGs. The input > + clock source could be 1 to 24 for CLK1 to CLK24. Zero means that the > + particular BRG will be driven by QE clock(BRGCLK). Should also have a clock-frequency property to specify what BRGCLK is. -Scott