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Date: Mon, 4 Feb 2008 14:30:04 -0600
From: Scott Wood <scottwood@freescale.com>
To: Anton Vorontsov <avorontsov@ru.mvista.com>
Subject: Re: [PATCH 08/11] [POWERPC] qe_lib: implement QE GTM support
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On Sun, Feb 03, 2008 at 08:10:19PM +0300, Anton Vorontsov wrote:
> GTM stands for General-purpose Timers Module and able to generate
> timer{1,2,3,4} interrupts.
> 
> There are several limitations in this support:
> 1. Cascaded (32 bit) timers unimplemented (1-2, 3-4).
>    This is straightforward to implement when needed, two timers should
>    be marked as "requested" and configured as appropriate.
> 2. Super-cascaded (64 bit) timers unimplemented (1-2-3-4).
>    This is also straightforward to implement when needed, all timers
>    should be marked as "requested" and configured as appropriate.

This isn't QE-specific; the same (as far as I see) timer hardware exists on,
for example, mpc8313 and mpc8349.

> +config QE_GTM
> +	bool
> +	help
> +	  QE General-Purpose Timers Module support

No bool text?

> +struct gtm_timer {
> +	unsigned int irq;
> +	bool requested;
> +
> +	u8 __iomem *gtcfr;
> +	u16 __iomem *gtmdr;
> +	u16 __iomem *gtpsr;
> +	u16 __iomem *gtcnr;
> +	u16 __iomem *gtrfr;
> +	u16 __iomem *gtevr;
> +};

__be16

> +static struct gtm_timer timers[4];
> +static struct qe_timers __iomem *qet;
> +static spinlock_t gtm_lock = __SPIN_LOCK_UNLOCKED(gtm_lock);

static DEFINE_SPINLOCK(gtm_lock);

Put these in a struct so multiple timer blocks can be supported (the non-QE
chips tend to have two blocks).

> +int qe_reset_ref_timer_16(int num, unsigned int hz, u16 ref)

What does this function do?  What goes in "hz" and "ref"?  Is it periodic or
one-shot?

-Scott