How to describe FPGA-based devices in the device tree ?

[Laurent Pinchart <laurentp@cse-semaphore.com>]

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Hi everybody,

I'm (at last) trying to move from ARCH=ppc to ARCH=powerpc. After reading 
Documentation/powerpc/booting-without-of.txt and various device trees in 
arch/powerpc/boot/dts, I still don't know how to express some devices in the 
device tree.

The target board has several devices on the processor local bus, as described 
in the following device tree fragment.

        localbus@f0010100 {
                compatible = "fsl,mpc8260-localbus",
                             "fsl,pq2-localbus";
                #address-cells = <2>;
                #size-cells = <1>;
                reg = <f0010100 60>;

                ranges = <0 0 40000000 01000000
                          2 0 f2000000 00100000
                          3 0 f3000000 00100000
                          4 0 f4000000 00100000>;

                flash@0,0 {
                        compatible = "cfi-flash";
                        reg = <0 0 01000000>;
                        bank-width = <2>;
                };

                nvram@2,0 {
                        compatible = "mtd-ram";
                        reg = <2 0 00100000>;
                        bank-width = <2>;
                };

                bcsr@3,0 {
                        device_type = "board-control";
                        reg = <3 0 00000020>;
                };

                fpga@4,0 {
                        reg = <4 0 00010000>;
                };
        };

The fourth device is a FPGA that contains several IP cores such as an 
interrupt controller and a SD/MMC host controller. If I understand things 
correctly, each IP core should have its own node in the device tree to allow 
proper binding with device drivers. As booting-without-of.txt describes the 
localbus node ranges as corresponding to a single chipselect and covering the 
entire chipselect access window, I can't have nodes for each IP core as 
children of the localbus node.

Should I put IP core nodes as children of the FPGA node ? If so, how do I map 
addresses at the FPGA level ? A ranges property in the FPGA node would let me 
map addresses in the FPGA scope to the localbus scope. However, as the 
localbus scope use the chipselect number as its first address cell and 0 as 
its second address cell, I don't see how I could translate offsets in the 
FPGA into an address at the localbus scope.

Could anyone advice me regarding how to properly describe my hardware in the 
device tree ?

Best regards,

-- 
Laurent Pinchart
CSE Semaphore Belgium

Chaussée de Bruxelles, 732A
B-1410 Waterloo
Belgium

T +32 (2) 387 42 59
F +32 (2) 387 42 75

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