Trouble with SCC UART ports when moving from ppc to powerpc

[Laurent Pinchart <laurentp@cse-semaphore.com>]

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Hi everybody,

I'm trying to move from ARCH=ppc to ARCH=powerpc on an MPC8272 based board.

I updated my bootloader (U-Boot) to get FDT support, wrote a device tree and 
compiled a powerpc kernel with CONFIG_PPC_CPM_NEW_BINDING set. No problem so 
far (well, no problem I haven't been able to solve).

I then tried to get the serial console on SCC1 to work. The serial port was 
silent, and the kernel hanged in cpm_uart_console_write while waiting for the 
CPM to clear the ready bit in tx buffer descriptors.

After checking the SCC1 configuration registers, parameter RAM and buffer 
descriptors, I found out that something was overwriting the buffer 
descriptors were stored in the DPRAM at offset 0.

Right after initializing the rx buffer descriptors, dumping the rx bds dpram 
with the BDI2000 gave me

90000088 003518e0 90000008 00351900
90000000 00351911 b5400000 2dace564

while I was expecting

90000088 003518e0 90000008 00351900
90000000 00351920 b0000000 00351940

Some data was clearly being overwritten by something.

The CPM dual port ram was defined in the device tree as follows (copied from 
the MPC8272ADS board device tree).

        muram@0 {
                #address-cells = <1>;
                #size-cells = <1>;
                ranges = <0 0 10000>;

                data@0 {
                        compatible = "fsl,cpm-muram-data";
                        reg = <0 2000 9800 800>;
                };
        };

Changing the reg property to

reg = <80 1f80 9800 800>;

fixed my problem.

Does anyone have any clue regarding what could write to the dpram ? I thought 
about some CPM peripheral set up by the boot loader, but my board 
initialization code calls cpm2_reset() long before initializing SCC1.

Best regards,

-- 
Laurent Pinchart
CSE Semaphore Belgium

Chaussée de Bruxelles, 732A
B-1410 Waterloo
Belgium

T +32 (2) 387 42 59
F +32 (2) 387 42 75

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