From: Josh Boyer <jwboyer@linux.vnet.ibm.com>
To: Stefan Roese <sr@denx.de>
Cc: linuxppc-dev@ozlabs.org
Subject: Re: [PATCH] [POWERPC] 4xx: Fix problem with new TLB storage attibute fields on 440x6 core
Date: Tue, 6 May 2008 10:01:17 -0500 [thread overview]
Message-ID: <20080506100117.22c88b09@zod.rchland.ibm.com> (raw)
In-Reply-To: <1209970399-4464-1-git-send-email-sr@denx.de>
On Mon, 5 May 2008 08:53:19 +0200
Stefan Roese <sr@denx.de> wrote:
> The new 440x6 core used on AMCC 460EX/GT introduces new storage attibure
> fields to the TLB2 word. Those are:
>
> Bit 11 12 13 14 15
> WL1 IL1I IL1D IL2I IL2D
>
> With these bits the cache (L1 and L2) can be configured in a more flexible
> way, instruction- and data-cache independently now. The "old" I and W bits
> are still available and setting these old bits will automically set these
> new bits too (for backward compatibilty).
>
> The current code does not clear these fields resulting in disabling the cache
> by chance. This patch now makes sure that these new bits are cleared when
> the TLB2 word is written.
>
> Signed-off-by: Stefan Roese <sr@denx.de>
Finally catching back up with email. This looks like .26 material,
correct?
josh
next prev parent reply other threads:[~2008-05-06 15:02 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-05-05 6:53 [PATCH] [POWERPC] 4xx: Fix problem with new TLB storage attibute fields on 440x6 core Stefan Roese
2008-05-06 15:01 ` Josh Boyer [this message]
2008-05-06 16:41 ` Stefan Roese
2008-05-06 19:41 ` Josh Boyer
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