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Date: Tue, 6 May 2008 10:01:17 -0500
From: Josh Boyer <jwboyer@linux.vnet.ibm.com>
To: Stefan Roese <sr@denx.de>
Subject: Re: [PATCH] [POWERPC] 4xx: Fix problem with new TLB storage
	attibute fields on 440x6 core
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On Mon,  5 May 2008 08:53:19 +0200
Stefan Roese <sr@denx.de> wrote:

> The new 440x6 core used on AMCC 460EX/GT introduces new storage attibure
> fields to the TLB2 word. Those are:
> 
> Bit  11   12   13   14   15
>      WL1  IL1I IL1D IL2I IL2D
> 
> With these bits the cache (L1 and L2) can be configured in a more flexible
> way, instruction- and data-cache independently now. The "old" I and W bits
> are still available and setting these old bits will automically set these
> new bits too (for backward compatibilty).
> 
> The current code does not clear these fields resulting in disabling the cache
> by chance. This patch now makes sure that these new bits are cleared when
> the TLB2 word is written.
> 
> Signed-off-by: Stefan Roese <sr@denx.de>

Finally catching back up with email.  This looks like .26 material,
correct?

josh