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From: Stefan Roese <sr@denx.de>
To: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Subject: Re: [PATCH] [POWERPC] 4xx: Fix problem with new TLB storage attibute
	fields on 440x6 core
Date: Tue, 6 May 2008 18:41:44 +0200
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On Tuesday 06 May 2008, Josh Boyer wrote:
> > The new 440x6 core used on AMCC 460EX/GT introduces new storage attibure
> > fields to the TLB2 word. Those are:
> >
> > Bit  11   12   13   14   15
> >      WL1  IL1I IL1D IL2I IL2D
> >
> > With these bits the cache (L1 and L2) can be configured in a more
> > flexible way, instruction- and data-cache independently now. The "old" I
> > and W bits are still available and setting these old bits will
> > automically set these new bits too (for backward compatibilty).
> >
> > The current code does not clear these fields resulting in disabling the
> > cache by chance. This patch now makes sure that these new bits are
> > cleared when the TLB2 word is written.
> >
> > Signed-off-by: Stefan Roese <sr@denx.de>
>
> Finally catching back up with email.  This looks like .26 material,
> correct?

Definitely, yes.

Best regards,
Stefan