Re: [PATCH 2/2] talitos: Freescale integrated security engine (SEC) driver

[Kim Phillips <kim.phillips@freescale.com>]

On Fri, 30 May 2008 22:09:04 +0400
Evgeniy Polyakov <johnpol@2ka.mipt.ru> wrote:

> Hi.
> 
> On Thu, May 29, 2008 at 02:12:50PM -0500, Kim Phillips (kim.phillips@freescale.com) wrote:
> 
> > +static irqreturn_t talitos_interrupt(int irq, void *data)
> > +{
> > +	struct device *dev = data;
> > +	struct talitos_private *priv = dev_get_drvdata(dev);
> > +
> > +	priv->status = in_be32(priv->reg + TALITOS_ISR);
> > +	priv->status_lo = in_be32(priv->reg + TALITOS_ISR_LO);
> > +
> > +	if (unlikely(priv->status & ~TALITOS_ISR_CHDONE)) {
> > +		talitos_error((unsigned long)data);
> > +		/* ack */
> > +		out_be32(priv->reg + TALITOS_ICR, priv->status);
> > +		out_be32(priv->reg + TALITOS_ICR_LO, priv->status_lo);
> > +	}
> > +	else
> > +	{
> > +		/* ack */
> > +		out_be32(priv->reg + TALITOS_ICR, priv->status);
> > +		out_be32(priv->reg + TALITOS_ICR_LO, priv->status_lo);
> > +
> > +		if (likely(priv->status & TALITOS_ISR_CHDONE))
> > +			tasklet_schedule(&priv->done_task);
> > +	}
> > +
> > +	return (priv->status || priv->status_lo) ? IRQ_HANDLED : IRQ_NONE;
> > +}
> 
> Don't you want to protect against simultaneous access to register space
> from different CPUs? Or it is single processor board only?

Doesn't linux mask the IRQ line for the interrupt currently being
serviced, and on all processors?

Kim