Virqs of cascaded interrupt controller.

Virqs of cascaded interrupt controller.

[Welch, Martyn (GE EntSol, Intelligent Platforms)]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain, Size: 1388 bytes --]

Hi,

I'm in the process of porting Linux to one of our boards based on an
8641D. Some of the interrupts of on-board devices are dealt with by a
custom interrupt controller in one of the onboard FPGAs, which cascades
into the 8641D's mpic. I'm trying to write a driver for it.

Looking at examples of cascaded interrupt handlers I've managed to get
to the point where the kernel is trying to register interrupts from the
DTB file I provide it. The problem is I don't know what virqs are being
assigned to the interrupts or how virqs are/should be assigned to a
cascaded interrupt controller.

Can anyone point me towards any documentation that my naïve googling is
missing or explain how this should work?

Martyn

----
Martyn Welch MEng MPhil MIET
Principal Software Engineer

GE Fanuc Intelligent Platforms
Tove Valley Business Park, Towcester,
Northants, NN12 6PF, United Kingdom

Telephone: +44 (0) 1327 359444
Direct Dial: +44 (0) 1327 322748
Fax: +44 (0) 1327 322800
email: martyn.welch@gefanuc.com
web: www.gefanuc.com

GE Fanuc Intelligent Platforms Ltd, registered in England and Wales
(3828642) at 100 Barbirolli Square, Manchester, M2 3AB, VAT GB 729 849
476  

GE Fanuc Intelligent Platforms Confidential and Proprietary. If you have
received this message in error please notify us immediately and
permanently remove it from your system and destroy any printed
hardcopies.    

Re: Virqs of cascaded interrupt controller.

[Scott Wood]

On Mon, Jun 23, 2008 at 03:00:35PM +0100, Welch, Martyn (GE EntSol, Intelligent Platforms) wrote:
> I'm in the process of porting Linux to one of our boards based on an
> 8641D. Some of the interrupts of on-board devices are dealt with by a
> custom interrupt controller in one of the onboard FPGAs, which cascades
> into the 8641D's mpic. I'm trying to write a driver for it.
> 
> Looking at examples of cascaded interrupt handlers I've managed to get
> to the point where the kernel is trying to register interrupts from the
> DTB file I provide it. The problem is I don't know what virqs are being
> assigned to the interrupts or how virqs are/should be assigned to a
> cascaded interrupt controller.

The virqs are created by irq_create_mapping() or irq_of_parse_and_map(). 
It is preferred to use the latter, with the interrupts expressed in the
device tree.

If that doesn't answer your question, could you be more specific about what
you're trying to find out, and/or what aspect of the existing cascaded irq
controllers (e.g. sysdev/qe_lib/qe_ic.c, platforms/82xx/pq2ads-pci-pic.c)
you want clarfication of?  Do you want to know what to pass to request_irq,
how to turn virqs back into hwirqs in the cascade driver, or something else?

-Scott