[PATCH] MPC52xx PCI write combine timer

[PATCH] MPC52xx PCI write combine timer

[Andre Schwarz]

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On MPC52xx the PCI target control register (PCITCR) @ MBAR + 0xD6C is initialized with
only bit 7 (Latrule disable) set. The 8-Bit write combine timer (Bits 24..31) should be
also set to a reasonable value _greater zero_ (0x08 = default) since setting it to 0x00
leads to _very poor_ performance as a PCI target since external burst won't be possible
at all.

Setting the WCT to 0x08 (cache-line size) leads to good overall perfomance.

Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
---



MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler  - Registergericht: Amtsgericht Stuttgart, HRB 271090
Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner

[-- Attachment #2: patch_mpc5200b_wct --]
[-- Type: text/plain, Size: 867 bytes --]

 arch/powerpc/platforms/52xx/mpc52xx_pci.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/powerpc/platforms/52xx/mpc52xx_pci.c b/arch/powerpc/platforms/52xx/mpc52xx_pci.c
index e3428dd..5a382bb 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_pci.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_pci.c
@@ -63,6 +63,7 @@
 
 #define MPC52xx_PCI_TCR_P		0x01000000
 #define MPC52xx_PCI_TCR_LD		0x00010000
+#define MPC52xx_PCI_TCR_WCT8		0x00000008
 
 #define MPC52xx_PCI_TBATR_DISABLE	0x0
 #define MPC52xx_PCI_TBATR_ENABLE	0x1
@@ -313,7 +314,7 @@ mpc52xx_pci_setup(struct pci_controller *hose,
 	out_be32(&pci_regs->tbatr1,
 		MPC52xx_PCI_TBATR_ENABLE | MPC52xx_PCI_TARGET_MEM );
 
-	out_be32(&pci_regs->tcr, MPC52xx_PCI_TCR_LD);
+	out_be32(&pci_regs->tcr, MPC52xx_PCI_TCR_LD | MPC52xx_PCI_TCR_WCT8);
 
 	tmp = in_be32(&pci_regs->gscr);
 #if 0

Re: [PATCH] MPC52xx PCI write combine timer

[Grant Likely]

On Thu, Jul 10, 2008 at 11:53:16AM +0200, Andre Schwarz wrote:
> On MPC52xx the PCI target control register (PCITCR) @ MBAR + 0xD6C is initialized with
> only bit 7 (Latrule disable) set. The 8-Bit write combine timer (Bits 24..31) should be
> also set to a reasonable value _greater zero_ (0x08 = default) since setting it to 0x00
> leads to _very poor_ performance as a PCI target since external burst won't be possible
> at all.
> 
> Setting the WCT to 0x08 (cache-line size) leads to good overall perfomance.

Looks good to me.  I'll test it here and pick it up if all looks good.

Cheers,
g.