From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from WA4EHSOBE002.bigfish.com (outbound-wa4.frontbridge.com [216.32.181.16]) by ozlabs.org (Postfix) with ESMTP id 7058DDE450 for ; Wed, 27 Aug 2008 02:41:10 +1000 (EST) MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----_=_NextPart_001_01C9079A.86DC7B11" Subject: RE: PPC405EP errata CPU 213 (Incorrect data may be flushed from thedata cache) Date: Tue, 26 Aug 2008 09:41:02 -0700 References: <1219766507.26004.92.camel@localhost> From: Stephen Neuendorffer To: "Darcy Watkins" , "linuxppc-embedded" Message-ID: <20080826164104.A31DA818052@mail1-wa4.bigfish.com> List-Id: Linux on Embedded PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , ------_=_NextPart_001_01C9079A.86DC7B11 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable arch/powerpc/boot/virtex405-head.S has: #include "ppc_asm.h" .text .global _zimage_start _zimage_start: /* PPC errata 213: needed by Virtex-4 FX */ mfccr0 0 oris 0,0,0x50000000@h mtccr0 0 So, this happens first before anything else. Without this, the boards that I've used crash pretty quickly, so it may be = obvious that the status register is set properly. As a result, you probably need to do it in the boot loader and not in the k= ernel proper. Steve -----Original Message----- From: linuxppc-embedded-bounces+stephen=3Dneuendorffer.name@ozlabs.org on b= ehalf of Darcy Watkins Sent: Tue 8/26/2008 9:01 AM To: linuxppc-embedded Subject: PPC405EP errata CPU 213 (Incorrect data may be flushed from thedat= a cache) = Hello, The IBM/AMCC errata document recommends setting reserved bits 1 & 3 in CCR0 as a workaround to PPC405EP errata CPU 213 (Incorrect data may be flushed from the data cache). For a start, I just tried hacking in a few lines of assembly code into... arch/powerpc/kernel/head_40x.S --- Around line #839 ... bl early_init /* We have to do this with MMU on */ /* * Decide what sort of machine this is and initialize the MMU. */ mr r3,r31 mr r4,r30 mr r5,r29 mr r6,r28 mr r7,r27 bl machine_init bl MMU_init /* DLW hack!! - for PPC405EP errata CPU 213 */ mfspr r4,SPRN_CCR0 oris r4,r4,0x5000 mtspr SPRN_CCR0,r4 isync /* Go back to running unmapped so we can load up new values * and change to using our exception vectors. * On the 4xx, all we have to do is invalidate the TLB to clear * the old 16M byte TLB mappings. */ lis r4,2f@h ... Since I am not a PowerPC assembler guru, does this appear right? I think that eventually I'd want to create a cpu_setup_40x.S with the fixup code as part of a setup_cpu_405ep function and then hook this into cputable.c, but first I want to make sure that the errata workaround is actually taking effect (and also not being undone by later startup code). -- = Regards, Darcy -------------- Darcy L. Watkins - Senior Software Developer Tranzeo Wireless Technologies, Inc. 19273 Fraser Way, Pitt Meadows, BC, Canada V3Y 2V4 T:604-460-6002 ext:410 http://www.tranzeo.com _______________________________________________ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded This email and any attachments are intended for the sole use of the named r= ecipient(s) and contain(s) confidential information that may be proprietary= , privileged or copyrighted under applicable law. If you are not the intend= ed recipient, do not read, copy, or forward this email message or any attac= hments. Delete this email message and any attachments immediately. ------_=_NextPart_001_01C9079A.86DC7B11 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable RE: PPC405EP errata CPU 213 (Incorrect data may be flushed from thed= ata cache)

arch/powerpc/boot/virtex405-head.S has:

#include "ppc_asm.h"

        .text
        .global _zimage_start
_zimage_start:

        /* PPC errata 213: needed by Vir= tex-4 FX */
        mfccr0  0
        oris    0,0,0x500= 00000@h
        mtccr0  0

So, this happens first before anything else.
Without this, the boards that I've used crash pretty quickly, so it may be = obvious that the status register is set properly.
As a result, you probably need to do it in the boot loader and not in the k= ernel proper.

Steve

-----Original Message-----
From: linuxppc-embedded-bounces+stephen=3Dneuendorffer.name@ozlabs.org on b= ehalf of Darcy Watkins
Sent: Tue 8/26/2008 9:01 AM
To: linuxppc-embedded
Subject: PPC405EP errata CPU 213 (Incorrect data may be flushed from thedat= a cache)

Hello,

The IBM/AMCC errata document recommends setting reserved bits 1 & 3 in<= BR> CCR0 as a workaround to PPC405EP errata CPU 213 (Incorrect data may be
flushed from the data cache).  For a start, I just tried hacking in a<= BR> few lines of assembly code into...

  arch/powerpc/kernel/head_40x.S

---

Around line #839 ...

        bl     = early_init      /* We have to do this with MMU on= */

/*
 * Decide what sort of machine this is and initialize the MMU.
 */
        mr     = r3,r31
        mr     = r4,r30
        mr     = r5,r29
        mr     = r6,r28
        mr     = r7,r27
        bl     = machine_init
        bl     = MMU_init
/* DLW hack!! - for PPC405EP errata CPU 213 */
        mfspr   r4,SPRN_CCR0         oris    r4,r4,0x5= 000
        mtspr   SPRN_CCR0,r4         isync

/* Go back to running unmapped so we can load up new values
 * and change to using our exception vectors.
 * On the 4xx, all we have to do is invalidate the TLB to clear
 * the old 16M byte TLB mappings.
 */
        lis     r4,2= f@h
...

Since I am not a PowerPC assembler guru, does this appear right?

I think that eventually I'd want to create a cpu_setup_40x.S with the
fixup code as part of a setup_cpu_405ep function and then hook this into cputable.c, but first I want to make sure that the errata workaround is
= actually taking effect (and also not being undone by later startup
code).

--


Regards,

Darcy

--------------
Darcy L. Watkins - Senior Software Developer
Tranzeo Wireless Technologies, Inc.
19273 Fraser Way, Pitt Meadows, BC, Canada V3Y 2V4
T:604-460-6002 ext:410
http://www.tranzeo.com


_______________________________________________
Linuxppc-embedded mailing list
Linuxppc-embedded@ozlabs.org
https://o= zlabs.org/mailman/listinfo/linuxppc-embedded


This email and any attachments are intended for the sole u= se of the named recipient(s) and contain(s) confidential information that m= ay be proprietary, privileged or copyrighted under applicable law. If you a= re not the intended recipient, do not read, copy, or forward this email mes= sage or any attachments. Delete this email message and any attachments imme= diately. ------_=_NextPart_001_01C9079A.86DC7B11--