From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from sunset.davemloft.net (unknown [74.93.104.97]) by ozlabs.org (Postfix) with ESMTP id 2D4EADDE1B for ; Sun, 26 Oct 2008 18:17:20 +1100 (EST) Date: Sun, 26 Oct 2008 00:16:56 -0700 (PDT) Message-Id: <20081026.001656.193696580.davem@davemloft.net> To: benh@kernel.crashing.org Subject: Re: [PATCH] genirq: Set initial default irq affinity to just CPU0 From: David Miller In-Reply-To: <1225003723.7654.490.camel@pasglop> References: <1224970389.7654.473.camel@pasglop> <4903A37A.50607@hypersurf.com> <1225003723.7654.490.camel@pasglop> Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Cc: linuxppc-dev@ozlabs.org, kevdig@hypersurf.com List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Benjamin Herrenschmidt Date: Sun, 26 Oct 2008 17:48:43 +1100 > > > What does this all mean to my GigE (dual 1.1 GHz 7455s)? Is this > > thing supposed to be able to spread irq between its cpus? > > Depends on the interrupt controller. I don't know that machine > but for example the Apple Dual G5's use an MPIC that can spread > based on an internal HW round robin scheme. This isn't always > the best idea tho for cache reasons... depends if an at what level > your caches are shared between CPUs. it's always going to be the wrong thing to do for networking cards, especially once we start doing RX flow seperation in software