Re: [PATCH] powerpc/4xx: Add L2 cache node to AMCC Canyonlands dts file

[Josh Boyer <jwboyer@linux.vnet.ibm.com>]

On Fri,  5 Dec 2008 07:08:52 +0100
Stefan Roese <sr@denx.de> wrote:

> With this patch the L2 cache is enabled on Canyonlands to increase the
> overall performance. There is a known cache coherency issue with the L2
> cache, but this is related to the high bandwidth (HB) PLB segment where
> the memory address is 0x8.xxxx.xxxx (low bandwidth PLB segment is mapped
> to 0x0.xxxx.xxxx). Since this HB address is currently unused it is safe
> to enable the L2 cache.
> 
> Signed-off-by: Stefan Roese <sr@denx.de>
> ---
>  arch/powerpc/boot/dts/canyonlands.dts |   10 ++++++++++
>  1 files changed, 10 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dts/canyonlands.dts
> index 79fe412..0d77482 100644
> --- a/arch/powerpc/boot/dts/canyonlands.dts
> +++ b/arch/powerpc/boot/dts/canyonlands.dts
> @@ -104,6 +104,16 @@
>  		dcr-reg = <0x00c 0x002>;
>  	};
> 
> +	L2C0: l2c {
> +		compatible = "ibm,l2-cache-460ex", "ibm,l2-cache";
> +		dcr-reg = <0x020 0x008		/* Internal SRAM DCR's */
> +			   0x030 0x008>;	/* L2 cache DCR's */
> +		cache-line-size = <32>;		/* 32 bytes */
> +		cache-size = <262144>;		/* L2, 256K */
> +		interrupt-parent = <&UIC1>;
> +		interrupts = <11 1>;
> +	};

Shouldn't there also be a next-level-cache property added to the cpu
node that references this?

josh